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ST7265x
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
DATASHEET
Memories - Up to 32K of ROM or High Density Flash (HDFlash) program memory with read/write protection - For HDFlash devices, In-Application Programming (IAP) via USB and In-Circuit programming (ICP) - Up to 5 Kbytes of RAM with up to 256 bytes stack s Clock, Reset and Supply Management - PLL for generating 48 MHz USB clock using a 12 MHz crystal - Low Voltage Reset (except on E suffix devices) - Dual supply management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices). - Programmable Internal Voltage Regulator for Memory cards (2.8V to 3.5V) supplying: Flash Card I/O lines (voltage shifting) Up to 50 mA for Flash card supply - Clock-out capability s 47 programmable I/O lines - 15 high sink I/Os (8mA @0.6V / 20mA@1.3V) - 5 true open drain outputs - 24 lines programmable as interrupt inputs s USB (Universal Serial Bus) Interface - with DMA for full speed bulk applications compliant with USB 12 Mbs specification (version 2.0 compliant) - On-Chip 3.3V USB voltage regulator and transceivers with software power-down - 5 USB endpoints: 1 control endpoint 2 IN endpoints supporting interrupt and bulk 2 OUT endpoints supporting interrupt and bulk - Hardware conversion between USB bulk packets and 512-byte blocks Device Summary
s
TQFP64 10x10
s
TQFP48
SO34 shrink
s
s
s
s
s
Mass Storage Interface - DTC (Data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards: Compact Flash - Multimedia Card Secure Digital Card - SmartMediaCard Sony Memory Stick - NAND Flash ATA Peripherals 2 Timers - Configurable Watchdog for system reliability - 16-bit Timer with 2 output compare functions. 2 Communication Interfaces - SPI synchronous serial interface - I2C Single Master Interface up to 400 KHz D/A and A/D Peripherals - PWM/BRM Generator (with 2 10-bit PWM/ BRM outputs) - 8-bit A/D Converter (ADC) with 8 channels Instruction Set - 8-bit data manipulation - 63 basic instructions - 17 main addressing modes - 8 x 8 unsigned multiply instruction - True bit manipulation Development Tools - Full hardware/software development package
Features Program memory User RAM (stack) - bytes Peripherals Operating Supply Package Operating Temperature June 2003
ST72651 32K ROM 5K (256)
ST72F651 32K FLASH
2
ST72652 16K ROM 512 (256) USB, DTC, WDT Single 4.0V to 5.5V TQFP64 (10 x10) / TQFP48 (7x7) / SO34
USB, DTC, Timer, ADC, SPI, I C, PWM, WDT Dual 2.7V to 5.5V or Dual 3.0V to 5.5V or 4.0V to 5.5V (for USB) 4.0V to 5.5V (for USB) TQFP64 (10 x10) 0C to +70C
Rev. 2.3
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This is preliminary information on a new product. Details are subject to change without notice.
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.7 IC SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 149 13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 159 15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 160 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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1 INTRODUCTION
The ST7265x MCU supports volume data exchange with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of handling various transfer protocols, with a particular emphasis on mass storage applications. ST7265x is compliant with the USB Mass Storage Class specifications, and supports related protocols such as BOT (Bulk Only Transfer) and CBI (Control, Bulk, Interrupt). It is based on the ST7 standard 8-bit core, with specific peripherals for managing USB full speed data transfer between the host and most types of FLASH media card: - A full speed USB interface with Serial Interface Engine, and on-chip 3.3V regulator and transceivers. Figure 1. USB Data Transfer Block Diagram USB SIE DATA TRANSFER BUFFER 512-byte RAM Buffer 512-byte RAM Buffer DATA TRANSFER COPROCESSOR (DTC) LEVEL SHIFTERS MASS STORAGE DEVICE - A dedicated 24 MHz Data Buffer Manager state machine for handling 512-byte data blocks (this size corresponds to a sector both on computers and FLASH media cards). - A Data Transfer Coprocessor (DTC), able to handle fast data transfer with external devices. This DTC also computes the CRC or ECC required to handle Mass storage media. - An Arbitration block gives the ST7 core priority over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC. - A FLASH Supply Block able to provide programmable supply voltage and I/O electrical levels to the FLASH media.
USB DATA TRANSFER BUFFER ACCESS ARBITRATION
ST7 CORE
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INTRODUCTION (Cont'd) In addition to the peripherals for USB full speed data transfer, the ST7265x includes all the necessary features for stand-alone applications with FLASH mass storage. - Low voltage reset ensuring proper power-on or power-off of the device (not on all products) - Digital Watchdog - 16-bit Timer with 2 output compare functions (not on all products - see device summary). - Two 10-bit PWM outputs (not on all products see device summary)
- Serial Peripheral interface (not on all products see device summary) - Fast I2C Single Master interface (not on all products - see device summary) - 8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs (not on all products see device summary) The ST72F65x are the Flash versions of the ST7265x in a TQFP64 package. The ST7265x are the ROM versions in a TQFP64 package.
Figure 2. Digital Audio Player Application Example in Play Mode DATA TRANSFER BUFFER 512-byte RAM Buffer 512-byte RAM Buffer
BUFFER ACCESS ARBITRATION
ST7 CORE
DATA TRANSFER COPROCESSOR (DTC)
I2C
LEVEL SHIFTERS
MASS STORAGE DEVICE
DIGITAL AUDIO DEVICE
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INTRODUCTION (Cont'd) Figure 3. ST7265x Block Diagram
OSCIN OSCOUT
12MHz OSC 48MHz PLL
CLOCK DIVIDER fCPU
PORT A PORT B SPI * PORT C
PA[7:0] (8 bits) PB[7:0] (8 bits)
PC[7:0] (8 bits)
ARBITRATION
DATA TRANSFER BUFFER (1280 bytes)
DATA TRANSFER COPROCESSOR DTC S/W RAM (256 Bytes) PORT E PWM* PORT F I C* 8-BIT ADC* VDDF VSSF VDDA VSSA VDD1,VDD2 DUAL SUPPLY MANAGER * VSS1, VSS2 USBVDD USBVSS
2
ADDRESS AND DATA BUS
PE[7:0] (8 bits)
USBDP USBDM USBVCC PD[7:0] (8 bits)
USB PORT D 16-BIT TIMER* WATCHDOG
PF[6:0] (7 bits)
RESET
CONTROL 8-BIT CORE ALU LVD* RAM (0.5/5 KBytes) PROGRAM MEMORY (16/32 Kbytes)
FLASH SUPPLY BLOCK POWER SUPPLY REGULATOR
VPP
* not on all products (refer to Table 1: Device Summary)
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2 PIN DESCRIPTION
Figure 4. 34-Pin SO Package Pinout
VSSA VSS2 OSCIN OSCOUT USBVSS USBDM USBDP USBVCC USBVDD VDDF VSSF DTC / PA0 DTC / PA1 DTC / PA2 DTC / PA3 MCO / (HS) PC0 DTC / (HS) PC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
ei0 ei1
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
ei2 ei2
VDDA VDD2 PF6 (HS) / ICCDATA PF5 (HS) / ICCCLK RESET VPP/ICCSEL PD6 PD5 PD4 PD3 PD2 PD1 PD0 VSS1 VDD1 PC3 (HS) / DTC PC2 (HS) / DTC
19 18
I/O pin supplied by VDDF / VSSF (HS) high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 5. 48-Pin TQFP Package Pinout
USBVSS USBDM USBDP USBVCC USBVDD VDDF VSSF DTC/PB0 DTC/PB1 DTC/PB2 DTC/PB3 DTC/PB4
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 ei1 29 8 28 9 27 10 ei0 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 DTC/PB5 DTC/PB6 DTC/PB7 DTC / PA0 DTC / PA1 DTC / PA2 DTC / PA3 DTC / PA4 DTC / PA5 DTC / PA6 DTC / PA7 VDD1
PF6 (HS) / ICCDATA PF5 (HS)/ICCCLK RESET VPP/ICCSEL PE4 PE3/DTC
OSCOUT OSCIN
VSS2 VSSA VDDA VDD2
PE2 (HS) / DTC PE1 (HS) / DTC PE0 (HS) / DTC PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VSS1
I/O pin supplied by VDDF / VSSF (HS) high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Figure 6. 64-Pin TQFP Package Pinout
OSCOUT OSCIN VSS2 VSSA VDDA VDD2 PF6 (HS)/ICCDATA PF5 (HS)/ICCCLK PF4 (HS) / USBEN PF3 / AIN1 PF2 / AIN0 PF1 (HS) / SDA PF0 (HS) / SCL RESET VPP/ICCSEL PE4 / PWM1 USBVSS USBDM USBDP USBVCC USBVDD VDDF VSSF DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS) DTC / PB0 DTC / PB1 DTC / PB2 DTC / PB3 DTC / PB4 DTC / PB5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 ei1 40 9 39 10 38 11 37 12 36 13 35 14 ei2 ei0 ei2 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PE3 / PWM0 / AIN7 / DTC PE2 (HS) / AIN6 / DTC PE1 (HS) / AIN5 / DTC PE0 (HS) / AIN4 / DTC PD7 / AIN3 PD6 / AIN2 PD5/OCMP2 PD4/OCMP1 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4
SS / MCO MISO / DTC MOSI / DTC SCK / DTC
DTC / PB6 DTC / PB7 DTC / PA0 DTC / PA1 DTC / PA2 DTC / PA3 DTC / PA4 DTC / PA5 DTC / PA6 DTC / PA7 / (HS) PC0 / (HS) PC1 / (HS) PC2 / (HS) PC3 VDD1 VSS1
I/O pin supplied by VDDF / VSSF (HS) high sink capability eix associated external interrupt vector
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PIN DESCRIPTION (Cont'd) Legend / Abbreviations: Type: I = input, O = output, S = supply VDDF powered: I/O powered by the alternate supply rail, supplied by VDDF and VSSF. In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High Sink (on N-buffer only)
Port and control configuration: - Input:float = floating, wpu = weak pull-up, int = interrupt - Output: OD = open drain, T = true open drain, PP = push-pull, OP = pull-up enabled by option byte. Refer to "I/O PORTS" on page 49 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold.
Table 1. Device Pin Description
VDDF Powered Pin TQFP48 TQFP64 Type SO34 Pin Name Level Output Input Port / Control Input float wpu int Output OD PP Main Function (after reset) Alternate Function
5 6 7
1 2 3
1 2 3
USBVSS USBDM USBDP
S I/O I/O
USB Digital ground USB bidirectional data (data -) USB bidirectional data (data +) USB power supply, output by the on-chip USB 3.3V linear regulator. Note: An external decoupling capacitor (typ. 100nF, min 47nF) must be connected between this pin and USBVSS. USB Power supply voltage (4V - 5.5V) Note: External decoupling capacitors (typ. 4.7F+100nF, min 2.2F+100nFmust be connected between this pin and USBVSS. Power Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator). Note: An external decoupling capacitor (min. 20nF) must be connected to this pin to stabilize the regulator. Ground Line for alternate supply rail. Can be used as input (with external supply) or output (when using the on-chip voltage regulator) DTC I/O with serial capability Port E5 (MMC_CMD) DTC I/O with serial capability Port E6 (MMC_DAT) DTC I/O with serial capability Port E7 (MMC_CLK) Port B0 Port B1 Port B2 DTC DTC DTC
8
4
4
USBVCC
O
9
5
5
USBVDD
S
10
6
6
VDDF
S
X
11 -
7 8 9 10
7 8 9 10 11 12 13
VSSF PE5/DTC PE6/DTC PE7/DTC PB0/DTC PB1/DTC PB2/DTC
S I/O I/O I/O I/O I/O I/O
X X CT HS X2 X CT HS X X CT HS X X X X C T C T C T X X X X2 X X X X X X X X
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VDDF Powered
Pin TQFP48 TQFP64 Type SO34 Pin Name
Level Output Input
Port / Control Input float wpu int Output OD PP Main Function (after reset) Alternate Function
12 13 14 15 16 17
11 12 13 14 15 16 17 18 19 20 21 22 23 -
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PB3/DTC PB4/DTC PB5/DTC PB6/DTC PB7/DTC PA0/DTC PA1/DTC PA2/DTC PA3/DTC PA4/DTC PA5/DTC PA6/DTC PA7/DTC PC0/MCO/SS PC1/DTC/MIS0
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
X X X X X X X X X X X X X X
C T C T C T C T C T C T C T C T C T C T C T C T C T C HS T
X X X X X X X X X X X X X X ei 0 X X X X X X X X
X X X X X X X X X X X X X X X ei 2
Port B3 Port B4 Port B5 Port B6 Port B7 Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port C0 Port C1
DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC DTC Main Clock Output / SPI Slave Select1 DTC I/O with serial capability (DATARQ) / SPI Master In Slave Out1 DTC I/O with serial capability (SDAT) / SPI Master Out Slave In1 DTC I/O with serial capability (SCLK) / SPI Serial Clock1
X CT HS X
18 19 20 21 -
24 25 -
29 30 31 32 33 34 35 36
PC2/DTC/MOSI PC3/DTC/SCK VDD1 VSS1 PC4/DTC PC5/DTC PC6/DTC PC7/DTC
I/O I/O S S I/O I/O I/O I/O
X CT HS X X CT HS X
X X
Port C2 Port C3
Power supply voltage (2.7V - 5.5V) Digital ground CT CT CT CT X X X X ei 2 X X X X Port C4 Port C5 Port C6 Port C7 DTC DTC DTC DTC
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VDDF Powered
Pin TQFP48 TQFP64 Type SO34 Pin Name
Level Output Input
Port / Control Input float wpu int Output OD PP Main Function (after reset) Alternate Function
22 23 24 25 26 27 28 29
26 27 28 29 30 31 32 33 34 35 36 37 38 39
37 38 39 40 41 42 43 44 45 46 47 48 49 50
PD0 PD1 PD2 PD3 PD4/OCMP1 PD5/OCMP2 PD6/AIN2 PD7/AIN3 PE0/DTC/AIN4 PE1/DTC/AIN5 PE2/DTC/AIN6 PE3/AIN7/DTC/ PWM0 PE4/PWM1 VPP /ICCSEL
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S
C T C T C T C T C T C T C T C T C HS T
X X X X X X X X X ei 1
X X X X X X X X X X X X X
X X X X X X X X X X X X X
Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7 Port E0 Port E1 Port E2 Port E3 Port E4 Timer Output Compare 11 Timer Output Compare 21 Analog Input 21 Analog Input 31 Analog Input 41/ DTC Analog Input 51/ DTC Analog Input 61/ DTC Analog Input 71/ DTC / PWM Output 01 PWM Output 11
CT HS X CT HS X CT CT X X
30
40
51
RESET
I/O
X
X
Flash programming voltage. Must be held low in normal operating mode. Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or VDD is low. It can be used to reset external peripherals. Port F0 Port F1 X X Port F2 Port F3 Port F4 Port F5 Port F6 I2C Serial Clock1 I2C Serial Data1 Analog Input 01 Analog Input 11 USB Power Management USB Enable (alternate function selected by option bit) ICC Clock Output ICC Data Input
31 32 33 34
41 42 43 44
52 53 54 55 56 57 58 59 60
PF0 / SCL PF1 / SDA PF2 / AIN0 PF3 / AIN1 PF4 / USBEN PF5 / ICCCLK PF6 / ICCDATA VDD2 VDDA
I/O I/O I/O I/O I/O I/O I/O S S
CT HS X CT HS X CT CT X X
T T
CT HS X CT HS X CT HS X
T T T
Main Power supply voltage (2.7V - 5.5V on devices without LVD, otherwise 4V - 5.5V). Analog supply voltage
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Pin TQFP48 TQFP64 Type SO34 Pin Name
Level Output Input
Port / Control Input float wpu int Output OD PP Main Function (after reset) Alternate Function
1 2 3 4
1 2
45 46 47 48
61 62 63 64
VSSA VSS2 OSCIN OSCOUT
S S I O
Analog ground Digital ground Input/Output Oscillator pins. These pins connect a 12 MHz parallel-resonant crystal, or an external source to the on-chip oscillator.
If the peripheral is present on the device (see Device Summary on page 1) A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register and depending on the PE5PU bit in the option byte.
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Figure 7. Multimedia Card Or Secure Digital Card Writer Application Example
4.7F 100nF
VDD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (2)
I/O LOGIC
LED1
LED2 DTC REGULATOR FLASH level translator
PE7 PE6 PE5 VPP
VDDF
12V for Flash prog. (connect to GND if not used)
CLK DAT CMD
100nF
VDD
UP TO 5 MULTIMEDIA OR SD CARDS
MultiMedia Card Pin ST72F65 pin ST7 / DTC (1) (1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. (2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
CMD PE5 DTC
DAT PE6 DTC
CLK PE7 DTC
used as a normal I/O by configuring it as such by the option byte.
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Figure 8. Smartmedia Card Writer Or Flash Drive Application Example
4.7F 100nF
VDD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (4) I/O LOGIC REGULATOR
LED1
DTC
LED2
5 level translator VDDF
PB PA PE
1
FLASH
VPP
12V for Flash prog. (connect to GND if not used)
8
100nF
I/O
6
2
CTRL
0~7
VDD
UP TO 2 SMARTMEDIA CARDS
Table 2. SmartMedia Interface Pin Assignment
SmartMedia Pin ST72F65 pin ST7 / DTC (1) I/O0~7 PB0-7 DTC CLE PA0 DTC WE PA1 DTC ALE PA2 DTC RE PA3 DTC R/B PA4 DTC WP(2) PA7 ST7 CE1(2) PE1 ST7 CE2(2)(3) PE0 ST7
(1): This line shows if the ST72F65 pin is controlled by the ST7 core or the DTC. (2): These lines are not controlled by the DTC but by the user software running on the ST7 core. The ST72F65 pin choice is at customer discretion. The pins shown here are only shown as an example. (3): When a single card is to be handled, PA7 is free for other functions. When 2 Smartmedia are to be handled, pins from both cards should be tied together (i.e. CLE1
with CLE2...) except for the CE pins. CE pin from card 1 should be connected to PA6 and CE pin from card 2 should be connect to PA7. Selection of the operating card is done by ST7 software. (4) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.
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Figure 9. Compact Flash Card Writer Application Example
4.7F 100nF
VDD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (3)
I/O LOGIC
REGULATOR LED1
LED2 DTC 12V for Flash prog. (connect to GND if not used)
1 5 level translator
PA PB PE [2]
4.7K
FLASH VDDF
VPP
6
8
4.7F
CF 8-BIT MEMORY MODE
100nF
Table 3. Compact Flash Card Writer Pin Assignment
IORD, Compact Flash RESET, D0-7 D8-15 CS1, INPACK, IOWR, REG, A0-2 GND, Card Pin CE2, VCC BVD1, BVD2 A3-10 VS1, VS2, WAIT, CSEL,
CE1
RE WE
CD1
CD2, RDY/BSY, WP NC -
ST72F65 pin ST7 / DTC (1)
PB0-7 DTC
NC -
NC -
VDDF Power
PE2 PA6 VSSF PA0-2 +pull-up PA3 PA5 +pull-up 4.7k 100k Power DTC ST7 DTC DTC ST7
(1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. (2) These lines are not controlled by the DTC but by the user software running on the ST7 core. The choice of ST72F65 pin is at the customer's discretion. The pins shown here are given only as an example.
(3) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.
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Figure 10. Sony Memory Stick Writer Application Example
4.7F 100nF
VDD
USBVDD =4.0-5.5V USB Port
5V
USBVDD
1.5K USB
VCC
100nF
DP DM GND DP DM USB GND
USB
POWER MANAGEMENT (2)
I/O LOGIC
LED1
LED2 DTC REGULATOR FLASH level translator
PC0 PC3 PC1 PC2 VPP
VDDF
12V for Flash prog. (connect to GND if not used)
CD CLK BS DAT 4.7F 100nF
VDD
SONY MEMORY STICK
MultiMedia Card Pin ST72F65 pin ST7 / DTC (1) (1) This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC. (2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
CMD PE5 DTC
DAT PE6 DTC
CLK PE7 DTC
used as a normal I/O by configuring it as such by the option byte.
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3 REGISTER & MEMORY MAP
As shown in Figure 11, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 80 bytes of register locations, up to 5 Kbytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. Figure 11. Memory Map
0050h 0000h 004Fh 0050h
The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations noted "Reserved" must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
HW Registers (see Table 4) 512 Bytes RAM*
00FFh 0100h 01FFh 0200h
Short Addressing RAM (176 Bytes) Stack (256 Bytes)
5 KBytes RAM* 144Fh 1450h DTC RAM (Write protected)
154Fh
256 Bytes USB Data Buffer** 1280 Bytes Reserved
16-bit Addressing RAM (80 Bytes)
024Fh
1A4Fh 7FFFh 8000h
0050h 00FFh 0100h 01FFh 0200h
Short Addressing RAM (176 Bytes) Stack (256 Bytes)
Program Memory* 32 Kbytes
C000h
16 Kbytes
144Fh FFDFh FFE0h
16-bit Addressing RAM (4688 Bytes)
FFFFh
Interrupt & Reset Vectors (see Table 10)
* Program memory and RAM sizes are product dependent (see Table -) ** The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in standalone mode.
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Table 4. Hardware Register Memory Map
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h to 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh DTC DSM SPI PCR SPIDR SPICR SPICSR DTCCR DTCSR Reserved DTCPR DTC Pointer Register 00h R/W Power Control Register SPI Data I/O Register SPI Control Register SPI Control/Status Register DTC Control Register DTC Status Register 00h 00h 00h xxh 0xh 00h R/W R/W R/W R/W R/W R/W Reserved Area (3 bytes) ADC1 WDG ADCDR ADCCSR WDGCR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR Block Register Label PADR PADDR PAOR PBDR PBDDR Register name Port A Data Register Port A Data Direction Register Port A Option Register Port B Data Register Port B Data Direction Register Reserved Area (1 byte) Port C Data Register Port C Data Direction Register Port C Option Register Port D Data Register Port D Data Direction Register Port D Option Register Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Reserved Area (1 byte) ADC Data Register ADC Control Status Register Watchdog Control Register 00h 00h 7Fh Read only R/W R/W 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Status 00h 00h 00h 00h 00h Remarks R/W R/W R/W R/W R/W
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Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh
Block
Register Label TCR1 TCR2 TSR CHR CLR
Register name Timer Control Register 1 Timer Control Register 2 Timer Status Register Timer Counter High Register Timer Counter Low Register Timer Alternate Counter High Register Timer Alternate Counter Low Register Timer Output Compare 1 High Register Timer Output Compare 1 Low Register Timer Output Compare 2 High Register Timer Output Compare 2 Low Register Flash Control Status Register
Reset Status 00h 00h 00h FFh FCh FFh FCh 80h 00h 80h 00h 00h FFh FFh FFh FFh 00h 00h 06h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Remarks R/W R/W Read Only Read Only Read Only Read Only Read Only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read only Read only R/W
TIM
ACHR ACLR OC1HR OC1LR OC2HR OC2LR
Flash ITSPR0 ITC ITSPR1 ITSPR2 ITSPR3 USBISTR USBIMR USBCTLR DADDR USBSR EP0R CNT0RXR USB CNT0TXR EP1RXR CNT1RXR EP1TXR CNT1TXR EP2RXR CNT2RXR EP2TXR CNT2TXR I2CCR I2CSR1 I2CSR2 I 2C 1 I2CCCR Not used Not used I2CDR USB BUFCSR
Interrupt Software Priority Register 0 Interrupt Software Priority Register 1 Interrupt Software Priority Register 2 Interrupt Software Priority Register 3 USB Interrupt Status Register USB Interrupt Mask Register USB Control Register Device Address Register USB Status Register Endpoint 0 Register EP 0 Reception Counter Register EP 0 Transmission Counter Register Endpoint 1 Register EP 1 Reception Counter Register Endpoint 1 Register EP 1 Transmission Counter Register Endpoint 2 Register EP 2 Reception Counter Register Endpoint 2 Register EP 2 Transmission Counter Register I2C
2
Control Register
I2C Status Register 1 I C Status Register 2 I2C Clock Control Register
I2C Data Register Buffer Control/Status Register Reserved Area (1 Byte)
00h 00h
R/W R/W
MISCR1 MISCR2
Miscellaneous Register 1 Miscellaneous Register 2 Reserved Area (1 Byte)
00h 00h
R/W R/W
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Address 004Ch 004Dh 004Eh 004Fh
Block
Register Label MISCR3 PWM0
Register name Miscellaneous Register 3 10-bit PWM/BRM registers
Reset Status 00h 80h 00h 80h
Remarks R/W R/W R/W R/W
PWM1
BRM10 PWM1
Note 1. If the peripheral is present on the device (see Device Summary on page 1)
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4 FLASH PROGRAM MEMORY
4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming). The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 Main Features
s
4.3 Structure The Flash memory is organised in sectors and can be used for both code and data storage. Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required. The first two sectors have a fixed size of 4 Kbytes (see Figure 12). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh). Table 5. Sectors available in Flash devices
Flash Memory Size (bytes) 4K 8K > 8K Available Sectors Sector 0 Sectors 0,1 Sectors 0,1, 2
s
s s
Three Flash programming modes: - Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased. - ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. - IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing
4.4 Program Memory Read-out Protection The read-out protection is enabled through an option bit. When this option is selected, the programs and data stored in the program memory (Flash or ROM) are protected against read-out piracy (including a re-write protection). In Flash devices, when this protection is removed by reprogramming the Option Byte, the entire program memory is first automatically erased and the device can be reprogrammed. Refer to the Option Byte description for more details.
Figure 12. Memory Map and Sector Address
4K
1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh
8K
10K
16K
24K
32K
48K
60K
DV FLASH MEMORY SIZE
SECTOR 2 2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes 52 Kbytes 4 Kbytes 4 Kbytes SECTOR 1 SECTOR 0
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FLASH PROGRAM MEMORY (Cont'd) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 13). For more details on the pin locations, refer to the device pinout description. ICP needs six pins to be connected to the programming tool. These pins are: - RESET: device reset - VSS: device power supply ground - ICCCLK: ICC output serial clock pin - ICCDATA: ICC input serial data pin Figure 13. Typical ICP Interface - ICCSEL/VPP: programming voltage - VDD: application board power supply CAUTIONS: 1. If RESET, ICCCLK or ICCDATA pins are used for other purposes in the application, a serial resistor has to be implemented to avoid a conflict in case one of the other devices forces the signal level. If these pins are used as outputs in the application, the serial resistors are not necessary. As soon as the external controller is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. 2. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. Please refer to the documentation of the tool. This pin must be connected when using ST Programming Tools (it is used to monitor the application power supply). Note: To develop a custom programming tool, refer to the ST7 Flash Programming and ICC Reference Manual which gives full details on the ICC protocol hardware and software.
PROGRAMMING TOOL
ICC CONNECTOR ICC Cable
OPTIONAL (SEE CAUTION 2)
ICC CONNECTOR HE10 CONNECTOR TYPE APPLICATION BOARD
9 10
7 8
5 6
3 4
1 2
10k APPLICATION POWER SUPPLY
>4.7k
VSS
ICCCLK
ICCSEL/VPP
ICCDATA
VDD
RESET
OPTIONAL (SEE CAUTION 1)
ST7
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FLASH PROGRAM MEMORY (Cont'd) 4.6 IAP (In-Application Programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 Related Documentation For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. Table 6. FLASH Register Map and Reset Values
Address (Hex.) 002Bh Register Label FCSR Reset Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0
4.8 Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read /Write Reset Value: 0000 0000 (00h)
7 0 0 0 0 0 0 0 0 0
This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.
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5 CENTRAL PROCESSING UNIT
5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES
s s s
5.3 CPU REGISTERS The 6 CPU registers shown in Figure 14 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).
s s s s s
Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts
Figure 14. CPU Registers
7 RESET VALUE = XXh 7 RESET VALUE = XXh 7 RESET VALUE = XXh 15 PCH 87 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 CONDITION CODE REGISTER 1 1 I1 H I0 N Z C RESET VALUE = 1 1 1 X 1 X X X 15 87 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 0 Y INDEX REGISTER 0 X INDEX REGISTER 0 ACCUMULATOR
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CENTRAL PROCESSING UNIT (Cont'd) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx
7
1 1 I1 H I0 N Z
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the "bit test and branch", shift and rotate instructions. Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1
0 C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It's a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.
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CENTRAL PROCESSING UNIT (Cont'd) Stack Pointer (SP) Read/Write Reset Value: 01 FFh
15 0 7
SP7 SP6 SP5 SP4 SP3 SP2 SP1
8 0 0 0 0 0 0 1 0 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 15). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Figure 15. Stack Manipulation Example
CALL Subroutine @ 0100h Interrupt Event PUSH Y
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 15. - When an interrupt is received, the SP is decremented and the context is pushed on the stack. - On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y
IRET
RET or RSP
SP SP CC A X PCH SP PCH @ 01FFh PCL PCL PCH PCL Y CC A X PCH PCL PCH PCL SP CC A X PCH PCL PCH PCL SP PCH PCL SP
Stack Higher Address = 01FFh Stack Lower Address = 0100h
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6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM 6.1.1 General Description The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the internal oscillator frequency (fOSC), which is 12 Mhz in Stand-alone mode and 48Mhz in USB mode. The internal clock (fCPU) is software selectable using the CP[1:0] and CPEN bits in the MISCR1 register. In USBVDD power supply mode, the PLL is active, generating a 48MHz clock to the USB. In this mode, fCPU can be configured to be up to 8 MHz. In VDD mode the PLL and the USB clock are disabled, and the maximum frequency of fCPU is 6 MHz. The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. The internal oscillator is designed to operate with an AT-cut parallel resonant quartz in the frequency range specified for fosc. The circuit shown in Figure 17 is recommended when using a crystal, and Table 7 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. 6.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 16. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING). Figure 16. External Clock Source Connections
OSCIN
OSCOUT NC
EXTERNAL CLOCK
Figure 17. Crystal Resonator
OSCIN
OSCOUT
Table 7. Recommended Values for 12-MHz Crystal Resonator
RSMAX COSCIN COSCOUT 20 56pF 56pF 25 47pF 47pF 70 22pF 22pF
COSCIN
COSCOUT
Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification).
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6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 6.2.2: s External RESET source pulse s Internal LVD RESET (Low Voltage Detection) s Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. Figure 18. RESET Sequences VDD
VIT+(LVD) VIT-(LVD)
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 18: s Active Phase depending on the RESET source s Min 512 CPU clock cycle delay (see Figure 20 and Figure 21 s RESET vector fetch
LVD RESET
SHORT EXT. RESET
LONG EXT. RESET
WATCHDOG RESET
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
ACTIVE PHASE
RUN
tw(RSTL)out th(RSTL)in
EXTERNAL RESET SOURCE
tw(RSTL)out th(RSTL)in
DELAY
tw(RSTL)out
RESET PIN
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (min 512 TCPU) VECTOR FETCH
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RESET SEQUENCE MANAGER (Cont'd) 6.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 18), the signal on the RESET pin will be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 18). Figure 19. Reset Block Diagram Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. 6.2.3 Internal Low Voltage Detection RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: s Power-On RESET s Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDDVDD
fCPU
COUNTER
INTERNAL RESET
RON
RESET
PULSE GENERATOR
WATCHDOG RESET LVD RESET
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RESET SEQUENCE MANAGER (Cont'd) In stand-alone mode, the 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state. Figure 20. Reset Delay in Stand-alone Mode
RESET
In USB mode the delay is 256 clock cycles counted from when the PLL LOCK signal goes high. The RESET vector fetch phase duration is 2 clock cycles.
DELAY
512 x tCPU(STAND-ALONE)
FETCH VECTOR
Figure 21. Reset Delay in USB Mode
RESET
DELAY
256 x tCPU(STAND-ALONE) PLL Startup time (undefined) 400 s typ.
256 x tCPU(USB) FETCH VECTOR
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
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6.3 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down, keeping the ST7 in reset. The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). Figure 22. Low Voltage Detector vs Reset VDD The LVD Reset circuitry generates a reset when VDD is below: - VIT+ when VDD is rising - VIT- when VDD is falling The LVD function is illustrated in Figure 22. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Vhyst VIT+(LVD) VIT-(LVD)
RESET
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6.4 POWER SUPPLY MANAGEMENT 6.4.1 Single Power Supply Management In applications operating only when connected to the USB (Flash writers, Backup systems), the microcontroller must operate from a single power supply (i.e. USB bus power supply or the local power source in the case of self-powered devices). Devices with LVD (no E suffix) or without LVD (E suffix) can support this configuration. In order to enable the Single Power Supply Management, the PLGIE bit in the PCR register should kept cleared by software (reset default value). In this case, pin VDD and USBVDD of the microcontroller must be connected together and supplied by a 4.0 to 5.5V voltage supply, either from the USB cable or from the local power source. See Figure 23. Figure 23. Single Power Supply Mode . troller can operate in two power supply modes: Stand-alone Mode and USB Mode. This configuration is only available on devices without LVD (E suffix). Devices with LVD are kept under reset when the power supply drops below the LVD threshold voltage and thus Stand-Alone mode can not be entered. In order to enable Dual Power Supply Management: - the USBEN pin function must be selected by programming the option byte. - the user software must set the PLGIE bit in the PCR register in the initialization routine. Stand-Alone Mode This mode is to be used when no USB communication is needed. The microcontroller in this mode can run at very low voltage, making the design of low power / battery supplied systems easy. In this mode: - The USB cable is unplugged (no voltage input on USBVDD pin) - The PLL is off - The on-chip USB interface is disabled - The core can run at up to 6 MHz internal frequency - USBEN is kept floating by H/W. - The microcontroller is supplied through the VDD pin USB Mode When connected to the USB, the microcontroller can run at full speed, still saving battery power by using USB power or self power source. To go into USB mode, a voltage from 4.0V to 5.5V must be provided to the USBVDD pin. In this mode: - The USB cable is plugged in - USBVDD pin is supplied by a 4.0 to 5.5V supply voltage, either from the USB cable or from the self powering source - The PLL is running at 48 MHz - The on-chip USB interface is enabled - The core can run at up to 8 MHz internal frequency - USBEN is set to output low level by hardware. This signal can be used to control an external transistor (USB SWITCH) to change the power supply configuration (see Figure 24). - The microcontroller can be USB bus powered
VDD1 VDD2 VDDA
USBVDD 4.0 - 5.5 V Note: Ground lines not shown In this mode: - The PLL is running at 48 MHz - The on-chip USB interface is enabled - The core can run at up to 8MHz internal frequency - The microcontroller can be either USB bus powered or supplied by the local power source (self powered) - The USBEN function is not used. The PF4 pin can be configured to work as a normal I/O by programming the Option Byte. 6.4.2 Dual Power Supply Management In case of a device that can be used both when powered by the USB or from a battery (Digital Audio Player, Digital Camera, PDA), the microconST7
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.2.1 Switching from Stand-Alone Mode to USB Mode In Stand-Alone Mode, when the user plugs in the USB cable, 4V min. is input to USBVDD. The onchip power Supply Manager generates an internal interrupt when USBVDD reaches USBVIT+ (if the PLGIE bit in the PCR register is set). The user program then can finish the current processing, and MUST generate a software RESET afterwards. This puts the microcontroller into reset state and all I/O ports go into input high impedance mode. Figure 24. External Power Supply Switch
Step-up converter
During and after this (software induced) reset phase, the USBEN pin is set to output low level by hardware. This causes the USB SWITCH to be turned ON. Consequently, VDD pin is powered by USBVDD supply. See Figure 24. Once in USB mode, no power is drawn from the step-up converter output. For more details, refer to Figure 25.
VDD1 VDD2 VDDA
PMOS
(Note 2) USB SWITCH Option bit
USBEN (True OD, H/W crtl)
General Purpose I/O (I/O port DR, DDR) Alternate Function (USBEN)
EDGE DETECTOR WITH LATCH Interrupt Request
USBVDD 4V min. from USB
USB VOLTAGE DETECTOR
VITPF VITMF PLG PLGIE
DETEN
PCR REGISTER
S/W RESET
USBVIT+ USBVIT-
RESET LOGIC
USBEN H/W CONTROL
ST7
USBVIT+ USBVITUSBVDD PLG bit VITMF Bit VITPF Bit
Note 1: Ground lines not shown Note 2: Suggested device: IRLML6302 (International rectifier) or Si230DS (Siliconix)
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.2.2 Switching from USB Mode to StandAlone Mode In USB Mode, when the user unplugs the USB cable, the voltage level drops on the USBVDD line. The on-chip Power Supply Manager generates a PLG interrupt when USBVDD reaches USBVIT-. The user program then can finish the current processing, and MUST generate a software RESET. Caution: Care should be taken as during this period the microcontroller clock is provided from the PLL output. Functionality in this mode is not guaranteed for voltages below VPLLmin. Software must ensure that the software RESET is generated before VDD. drops below VPLLmin. Failing to do this will cause the clock circuitry to stop, freezing the microcontroller operations. Once the user program has executed the software reset, the microcontroller goes into reset state and all I/O ports go into floating input mode.
During and after this (software induced) reset phase, the USBEN pin is put in high impedance by hardware. It causes the USB SWITCH to be turned OFF, so USBVDD is disconnected from VDD. The PLL is automatically stopped and the internal frequency is provided by a division of the crystal frequency. Refer to Figure 25. The microcontroller is still powered by the residual USBVDD voltage (higher than step-up converter set output level). This VDD voltage decreases during the reset phase until it reaches the step-up converter set output voltage. At that time, step-up converter resumes operation, and powers the application. Caution: In order to avoid applying excessive voltage to the Storage Media, a minimum delay must be ensured during (and after if needed) the reset phase, prior to switching ON the external STORAGE switch. See Figure 26 and Figure 27.
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POWER SUPPLY MANAGEMENT (Cont'd) Figure 25. Power Supply Management: Dual Power Supply
STAND-ALONE SUPPLY SUPPLY VOLTAGES USBVIT+ USBVITVPLLmin48
USBVDD
PLG INTERRUPT REQUEST RESET S/W STATUS
RESET
STAND-ALONE PROCESSING
1
2
RESET
USB MODE PROCESS.
1 2 RST STAND-ALONE MODE RESET PROCESSING
S/W Reset
S/W Reset
USBEN
HI-Z
ON
HI-Z
USB MODE VIT+(LVD) STAND-ALONE STAND-ALONE VIT-(LVD)
VDD pin
voltage PLL ON/OFF 48 MHz SIGNAL CLOCK SOURCE
PLL OFF
PLL ON
PLL OFF
NO CLOCK
UNDE 3 FINED
STABLE 48 MHz 4
NO CLOCK
CRYSTAL (12MHz)
PLL
CRYSTAL (12MHz)
1. Interrupt processing 2. Finish current processing 3. PLL start-up time (automatically controlled by hardware following a software reset) 4. PLL running with frequency in the range of 48 to 24 MHz (see section 13.3.3 on page 131)
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.3 Storage Media Interface I/Os The microcontroller is able to drive Storage Media through an interface operating at a different voltage from the rest of the circuit. This is achieved by powering the Storage Media interface I/O circuitry through a specific supply rail connected to VDDF pin. The VDDF pin can be used either as an input or output. If the on-chip voltage regulator is off, power to the interface I/Os should be provided externally to the VDDF pin. This should be the case when in StandAlone Mode, or in USB mode when the current required to power the Storage Media is above the current capacity of the on-chip regulator. If the on-chip voltage regulator is on, it powers the interface I/Os, and VDDF pin can supply the Storage Media. This is recommended in USB Mode, when the current required to power the Storage Media is within the capacity of the on-chip regulator. Application Example: Stand-Alone Mode - The Storage Media interface supply is powered by VDD enabled by an external switch (see Figure 26) which connects VDD to VDDF. This switch can be driven by any True Open Drain I/O pin and controlled by user software. - The on-chip voltage regulator must be disabled to avoid any conflict and to decrease consumption (reset the REGEN bit in the PCR register).
USB Mode - In this case the core of the microcontroller is running from the USB bus power or the self power supply. VDD and USBVDD pins are supplied with a voltage from 4.0 to 5.5V. - The Storage Media Interface can be powered through the on-chip regulator (providing power to the I/O pins and output on pin VDDF) if the current requirement is within the output capacity of the on chip regulator. - The regulator output voltage can be programmed to 2.8V, 3.3V, 3.4V or 3.5 Volts, depending on the Storage Media specifications. (see VSET[1:0] bits in PCR register description) - Should the current requirement for the Storage Media be higher than the current capacity of the on chip regulator, an external regulator should be used (See Figure 27). Thus the on-chip voltage regulator must be disabled to avoid any conflict (reset the REGEN bit in the PCR register). Caution: The user should ensure that VDD does not exceed the maximum rating specified for the Storage Media VDDF max when switching STORAGE switch on.
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POWER SUPPLY MANAGEMENT (Cont'd) Figure 26. Storage Media Interface Supply Switch (for low current Media)
VDD (2.7V - 5.5V)
This Switch is turned ON to power Storage Media I/F in Stand-Alone Mode
VDD1 VDD2 VDDA
PMOS
STORAGE SWITCH The on-chip Regulator supplies the Storage Media I/F in USB mode
I/O pin (True OD) VDDF
VOLTAGE REGULATOR 2.8V, 3.3V, 3.4V or 3.5V
STORAGE MEDIA
STORAGE MEDIA I/Os LEVEL TRANSLATOR
I/O LOGIC
ST7 Note: Ground lines not shown Figure 27. Storage Media Interface Supply Switch (for high current Media) VDD (2.7V - 5.5V)
This Switch is turned ON to power Storage Media I/F in Stand-Alone Mode
VDD1 VDD2 VDDA
PMOS
STORAGE SWITCH
This Regulator supplies the Storage Media I/F in USB Mode
REGUL
I/O pin (True OD) VDDF
This supply is not used and MUST be disabled
VOLTAGE REGULATOR 2.8V, 3.3V, 3.4V or 3.5V
STORAGE MEDIA
STORAGE MEDIA I/Os LEVEL TRANSLATOR
I/O LOGIC
ST7 Note: Ground lines not shown
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.4 Power Management Application Example In the example shown in Figure 28, the VDD supply is provided by a step up. In this case the step up
must be capable of tolerating voltages up to 5.5V on its Vout pin.
Figure 28. Dual Power Supply Application Example (low current Storage Media)
50H
Step Up
USBVDD Switch USBEN USBVDD =4.0-5.5V USB port
5V DP DM GND USBVDD
1.2V
10F
VDD
4.7F
USB VCC
USB
DP DM USB GND
POWER MANAGEMENT
DEC Switch
I/O LOGIC
Audio AMP
2
I2C
I2C
KEYBOARD
DAC THRESH LED
I2S
MPEG Decoder
STA013
DTC
4
FLASH MP3
1.5Mbit/s Max
REGULATOR level translator Cbus=40pF max VDDF
VPP
12V for Flash prog.
100nF LCD DISPLAY STORAGE MEDIA LIGHT
4.7F
STORAGE Switch
TDA7474
2M - 128MByte
Vdd in Stand-Alone mode Regulator output (2.8 - 3.5V) in USB mode
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POWER SUPPLY MANAGEMENT (Cont'd) 6.4.5 Register Description POWER CONTROL REGISTER (PCR) Reset Value: 0000 0000 (00h)
7 ITPF ITM F PLG PLG IE VSE T1 VSE T0 DET EN 0 REG EN
Bit 3:2 = VSET[1:0] Voltage Regulator Output Voltage. These bits are set and cleared by software to select the output voltage of the on-chip voltage regulator (for the VDDF output).
VSE VSE T1 T0 0 0 0 1 1 0 1 1 Voltage output of the regulator 3.5V 3.4V 3.3V 2.8V
Bit 7 = ITPF Voltage Input Threshold Plus Flag This bit is set by hardware when USBVDD rises over USBVIT+ and cleared by hardware when USBVDD drops below USBVIT+. 0: USBVDD < USBVIT+ 1:USBVDD > USBVIT+ Bit 6 = ITMF Voltage Input Threshold Minus Flag This bit is set by hardware when USBVDD rises over USBVIT- and cleared by hardware when USBVDD drops below USBVIT-. 0: USBVDD < USBVIT1:USBVDD > USBVITBit 5 = PLG USB Plug/Unplug detection. This bit is set by hardware when it detects that the USB cable has been plugged in. It is cleared by hardware when the USB cable is unplugged. (Detection happens when USBVDD rises over USBVIT+ or when USBVDD drops below USBVIT-). If the PLGIE bit is set, the rising edge of the PLG bit also generates an interrupt request. 0: USB cable unplugged 1: USB cable plugged in Bit 4 = PLGIE USB Plug/Unplug Interrupt Enable. This bit is set and cleared by software. 0: Single supply mode: PLG interrupt disabled. 1: Dual supply mode: PLG interrupt enabled (generates an interrupt on the rising edge of PLG).
Bit 1 = DETEN USB Voltage Detector Enable. This bit is set and cleared by software. It is used to power-off the USB voltage detector in Stand-alone mode. 0: The USB voltage detector is enabled. 1: The USB voltage detector disabled (ITPF, ITMF and PLG bits are forced high) Bit 0 = REGEN Voltage Regulator Enable. This bit is set and cleared by software. 0: The regulator is completely shutdown and no current is drawn from the power supply by the voltage reference. 1: The on-chip voltage regulator is powered-on.
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7 INTERRUPTS
7.1 INTRODUCTION The CPU enhanced interrupt management provides the following features: s Hardware interrupts s Software interrupt (TRAP) s Nested or concurrent interrupt management with flexible interrupt priority and level management: - Up to 4 software programmable nesting levels - Up to 16 interrupt vectors fixed by hardware - 3 non maskable events: RESET, TRAP, TLI This interrupt management is based on: - Bit 5 and bit 3 of the CPU CC register (I1:0), - Interrupt software priority registers (ISPRx), - Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to FFFFh) sorted by hardware priority order. This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) CPU interrupt controller. 7.2 MASKING AND PROCESSING FLOW The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of each interrupt vector (see Table 8). The processing flow is shown in Figure 29. Figure 29. Interrupt Processing Flowchart
RESET PENDING INTERRUPT N Y TLI Interrupt has the same or a lower software priority than current one N I1:0 Interrupt has a higher software priority than current one Y
When an interrupt request has to be serviced: - Normal processing is suspended at the end of the current instruction execution. - The PC, X, A and CC registers are saved onto the stack. - I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector. - The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to "Interrupt Mapping" table for vector addresses). The interrupt service routine should end with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume. Table 8. Interrupt Software Priority Levels
Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Level Low I1 1 0 0 1 I0 0 1 0 1
High
FETCH NEXT INSTRUCTION
THE INTERRUPT STAYS PENDING
Y
"IRET" N
RESTORE PC, X, A, CC FROM STACK
EXECUTE INSTRUCTION
STACK PC, X, A, CC LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR
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INTERRUPTS (Cont'd) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: - the highest software priority interrupt is serviced, - if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 30 describes this decision process. Figure 30. Priority Decision Process
PENDING INTERRUPTS
TLI (Top Level Hardware Interrupt) This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. Caution: A TRAP instruction must not be used in a TLI service routine. s TRAP (Non Maskable Software Interrupt) This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in Figure 29 as a TLI. Caution: TRAP can be interrupted by a TLI. s RESET The RESET source has the highest priority in the CPU. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority. See the RESET chapter for more details.
s
Same
SOFTWARE PRIORITY
Different
HIGHEST SOFTWARE PRIORITY SERVICED HIGHEST HARDWARE PRIORITY SERVICED
When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. Note 2: RESET, TRAP and TLI can be considered as having the highest software priority in the decision process. Different Interrupt Vector Sources Two interrupt source types are managed by the CPU interrupt controller: the non-maskable type (RESET, TRAP, TLI) and the maskable type (external or from internal peripherals). Non-Maskable Sources These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see Figure 29). After stacking the PC, X, A and CC registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to disable interrupts (level 3). These sources allow the processor to exit HALT mode.
Maskable Sources Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending. s External Interrupts External interrupts allow the processor to exit from HALT low power mode. External interrupt sensitivity is software selectable through the ISx bits in the MISCR1 and MISCR3 registers. External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically NANDed. s Peripheral Interrupts Usually the peripheral interrupts cause the Device to exit from HALT mode except those mentioned in the "Interrupt Mapping" table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont'd) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column "Exit from HALT" in "Interrupt Mapping" table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in Figure 30. Note: If an interrupt, that is not able to Exit from HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced. Figure 31. Concurrent Interrupt Management
SOFTWARE PRIORITY LEVEL IT2 IT1 IT4 IT3 TLI IT0 I1 I0
7.4 CONCURRENT & NESTED MANAGEMENT The following Figure 31 and Figure 32 show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure 32. The interrupt hardware priority is given in this order from the lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for each interrupt. Warning: A stack overflow may occur without notifying the software of the failure.
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN MAIN IT1
3 3 3 3 3 3 3/0 10
11 11 11 11 11 11
11 / 10 Figure 32. Nested Interrupt Management
SOFTWARE PRIORITY LEVEL
IT0
IT2
IT1
IT4
IT3
TLI
I1
I0
HARDWARE PRIORITY
TLI IT0 IT1 IT2 IT3 RIM IT4 MAIN IT4 MAIN IT1 IT2
3 3 2 1 3 3 3/0 10
11 11 00 01 11 11
11 / 10
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USED STACK = 20 BYTES
USED STACK = 10 BYTES
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INTERRUPTS (Cont'd) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read /Write Reset Value: 111x 1010 (xAh)
7 1 1 I1 H I0 N Z 0 C ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I0_9 I1_4 I1_8 I0_4 I0_8
INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh)
7 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 0 I0_0
Bit 5, 3 = I1, I0 Software Interrupt Priority These two bits indicate the current interrupt software priority.
Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable*) Level Low I1 1 0 0 1 I0 0 1 0 1
ISPR2 ISPR3
I1_11 I0_11 I1_10 I0_10 I1_9 1 1 1 1
I1_13 I0_13 I1_12 I0_12
High
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see "Interrupt Dedicated Instruction Set" table). *Note: TLI, TRAP and RESET events can interrupt a level 3 program.
These four registers contain the interrupt software priority of each interrupt vector. - Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.
Vector address FFFBh-FFFAh FFF9h-FFF8h ... FFE1h-FFE0h ISPRx bits I1_0 and I0_0 bits* I1_1 and I0_1 bits ... I1_13 and I0_13 bits
- Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register. - Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant in the interrupt process management. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).
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INTERRUPTS (Cont'd) Table 9. Dedicated Interrupt Instruction Set
Instruction HALT IRET JRM JRNM POP CC RIM SIM TRAP WFI New Description Entering Halt mode Interrupt routine return Jump if I1:0=11 Jump if I1:0<>11 Pop CC from the Stack Enable interrupt (level 0 set) Disable interrupt (level 3 set) Software trap Wait for interrupt Function/Example Pop CC, A, X, PC I1:0=11 ? I1:0<>11 ? Mem => CC Load 10 in I1:0 of CC Load 11 in I1:0 of CC Software NMI I1 1 I1 H H I0 0 I0 N N Z Z C C
I1 1 1 1 1
H
I0 0 1 1 0
N
Z
C
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions. In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions should never be used in an interrupt routine. Table 10. Interrupt Mapping
N Source Block RESET TRAP ICP PLG EI0 DTC USB ESUSP EI1 I2 C TIM EI2 SPI Description Reset Software Interrupt Flash Start Programming NMI Interrupt Power Management USB Plug/Unplug External Interrupt Port A DTC Peripheral Interrupt USB Peripheral Interrupt USB End Suspend Interrupt External Interrupt Port D I2C Interrupt Timer interrupt External Interrupt Port C SPI interrupt Register Label Priority Order Highest Priority Exit from HALT yes no yes yes yes no no yes yes no no yes yes Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h
N/A PCR N/A DTCSR USBISTR USBISTR N/A I2CSRx TSR N/A SPICSR
0 1 2 3 4 5 6 7 8 9 10
Lowest Priority
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INTERRUPTS (Cont'd) Table 11. Nested Interrupts Register Map and Reset Values
Address (Hex.) 002Ch Register Label ISPR0 Reset Value ISPR1 Reset Value ISPR2 Reset Value ISPR3 Reset Value 7 DTC I1_3 1 I2C 002Dh I1_7 I0_7 1 1 Not used I1_11 1 I0_11 1 I1_6 1 SPI I1_10 1 I0_10 1 I1_9 1 I0_3 1 I1_2 1 EI1 I0_6 1 6 5 EI0 I0_2 1 I1_1 1 I1_5 1 EI2 I0_9 1 I1_8 1 4 3 PLG I0_1 1 I0_5 1 1 USB I1_4 1 TIM I0_8 1 I0_4 1 2 1 ISP 1 0
ESUSP
002Eh
002Fh
1
1
1
1
Not used I1_13 I0_13 1 1
Not used I1_12 I0_12 1 1
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8 POWER SAVING MODES
8.1 INTRODUCTION To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7. After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (fCPU). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status. The user can also switch off any unused on-chip peripherals individually by programming the MISCR2 register. 8.2 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the "WFI" ST7 software instruction. All peripherals remain active. During WAIT mode, the I1:0] bits in the CC register are forced to 0, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine. The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 33.
N INTERRUPT
Figure 33. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
ON ON OFF CLEARED
N RESET
Y
Y
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
ON ON ON SET
IF RESET DELAY (Refer to Figure 20 and Figure 21)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I1:0] bits are set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont'd) 8.3 HALT MODE The HALT mode is the MCU lowest power consumption mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. When entering HALT mode, the I[1:0] bits in the Condition Code Register are cleared. Thus, any of the external interrupts (ITi or USB end suspend mode), are allowed and if an interrupt occurs, the CPU clock becomes active. The MCU can exit HALT mode on reception of either an external interrupt on ITi, an end suspend mode interrupt coming from USB peripheral, an SPI interrupt or a reset. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 512 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up. Figure 34. HALT Mode Flow Chart
HALT INSTRUCTION
OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS
OFF OFF OFF CLEARED
N RESET N
EXTERNAL INTERRUPT*
Y
Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I1:0] BITS ON ON ON SET
DELAY (Refer to Figure 20 and Figure 21)
FETCH RESET VECTOR OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. TheI1:0] bits are set during the interrupt routine and cleared when the CC register is popped.
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9 I/O PORTS
9.1 INTRODUCTION Important note: Please note that the I/O port configurations of this device differ from those of the other ST7 devices. The I/O ports offer different functional modes: - transfer of data through digital inputs and outputs and for specific pins: - external interrupt generation - alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.2 FUNCTIONAL DESCRIPTION Each port has 2 main registers: - Data Register (DR) - Data Direction Register (DDR) and one optional register: - Option Register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 35 9.2.1 Input Modes The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register. Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed and inverted. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 36). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified. 9.2.2 Output Modes Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:
DR 0 1 Push-pull VSS VDD Open-drain Vss Floating
The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Reading the DR register returns the digital value present on the external I/O pin. Consequently even in output mode a value written to an open drain port may differ from the value read from the port. For example, if software writes a `1' in the latch, this value will be applied to the pin, but the pin may stay at `0' depending on the state of the external circuitry. For this reason, bit manipulation even using instructions like BRES and BSET must not be used on open drain ports as they work by reading a byte, changing a bit and writing back a byte. A workaround for applications requiring bit manipulation on Open Drain I/Os is given in Section 9.2.4.
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I/O PORTS (Cont'd) 9.2.3 Alternate Functions When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input. It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin. WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.
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I/O PORTS (Cont'd) Figure 35. I/O Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT 1 VDD 0 ALTERNATE ENABLE DR
P-BUFFER (see table below) PULL-UP (see table below) VDD
DDR PULL-UP CONFIGURATION If implemented OR SEL N-BUFFER DDR SEL CMOS SCHMITT TRIGGER ANALOG INPUT DIODES (see table below) PAD
OR
EXTERNAL INTERRUPT SOURCE (eix)
Table 12. I/O Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up Off On Off NI P-Buffer Off On Off NI On On Diodes to VDD to VSS
Output
Legend: NI - not implemented Off - implemented not activated On - implemented and activated Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the device against positive stress.
DATA BUS
DR SEL
ALTERNATE INPUT FROM OTHER BITS
POLARITY SELECTION
NI (see note)
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I/O PORTS (Cont'd) Table 13. I/O Port Configurations
Hardware Configuration
NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS VDD RPU PAD PULL-UP CONFIGURATION DR REGISTER ACCESS
DR REGISTER
W DATA BUS R
INPUT 1)
ALTERNATE INPUT FROM OTHER PINS INTERRUPT CONFIGURATION POLARITY SELECTION ANALOG INPUT NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS EXTERNAL INTERRUPT SOURCE (eix)
OPEN-DRAIN OUTPUT 2)
VDD RPU
DR REGISTER ACCESS
R DR REGISTER W
PAD DATA BUS
ALTERNATE ENABLE NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS
ALTERNATE OUTPUT DR REGISTER ACCESS
PUSH-PULL OUTPUT 2)
VDD RPU
R DR REGISTER W
PAD DATA BUS
ALTERNATE ENABLE
ALTERNATE OUTPUT
Notes: 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. 2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont'd) 9.2.4 Bit manipulation on Open Drain Outputs As mentioned in Section 9.2.2, software should avoid using bit manipulation instructions on the DR register in open drain output mode, but must always access it using byte instructions. If bit manipulation is needed, the solution is to use a copy of the DR register in RAM, change the bits (using BRES or BCLR instructions for example) and copy the whole byte into the DR register each time the value has to be output on a port. This way, no bit manipulation is performed on the DR register but each bit of the DR register can be controlled separately. 9.3 I/O PORT IMPLEMENTATION The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Port B (without Option Register) PB[7:0]
MODE floating input push-pull output DDR 0 1
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 36. Interrupt I/O Port State Transitions
01
INPUT floating/pull-up interrupt
00
INPUT floating (reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX
= DDR, OR
The I/O port register configurations are summarized as follows.
Table 14. Port Configuration (with Option Register)
Port Port A Pin name PA7:0 PC7:4 Port C PC3:0 Port D PD7:0 PE7:6 PE5 PE4:3 PE2:0 PF6:4 PF3:2 PF1:0 floating floating floating Input OR = 0 floating floating OR = 1 floating with interrupt floating with interrupt floating with interrupt floating with interrupt floating with pull-up, if selected by option byte see Section 15.1) floating floating floating floating floating OR = 0 open drain push-pull push-pull open drain push-pull Output OR = 1 push-pull High-Sink No No Yes No Yes Yes No Yes Yes No Yes
Port E
Port F
open drain push-pull open drain (with pull-up, if selectpush-pull ed by option byte see Section 15.1) open drain push-pull open drain push-pull True open drain push-pull True open drain
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I/O PORTS (Cont'd) 9.4 Register Description DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
OPTION REGISTER (OR) Port x Option Register PxOR with x = A, C, D, or E Read /Write Reset Value: 0000 0000 (00h)
7 O7 O6 O5 O4 O3 O2 O1 0 O0
Bits 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register always returns the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read /Write Reset Value: 0000 0000 (00h)
7 DD7 DD6 DD5 DD4 DD3 DD2 DD1 0 DD0
Bits 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration. The OR register allows to distinguish: in input mode if the interrupt capability or the basic configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Floating input with interrupt (ports A, C and D). For port E configuration, refer to Table 14. Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull
Bits 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
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I/O PORTS (Cont'd) Table 15. I/O Port Register Map and Reset Values
Address (Hex.) Reset Value of all I/O port 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h Register Label registers PADR PADDR PAOR PBDR PBDDR PCDR PCDDR PCOR PDDR PDDDR PDOR PEDR PEDDR PEOR PFDR PFDDR 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
MSB
LSB
MSB Unused MSB
LSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
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10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1) Read /Write Reset Value: 0000 0000 (00h)
7 IS11 IS10 MCO IS21 IS20 CP1 0 Operating Mode CP0 CPEN Stand-alone mode (fOSC = 12 MHz) fCPU 3 MHz 6 MHz* 1.5 MHz 750 KHz 375 KHz 6 MHz 8 MHz 2 MHz 1 MHz 250 KHz CP1 CP0 CPEN x x 0 0 0 1 1 0 1 0 1 1 1 1 1 x x 0 0 0 1 1 0 1 0 1 1 1 1 1
Bits 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the CPEN bit. These two bits are set and cleared by software
Bits 7:6 = IS1[1:0] ei0 Interrupt sensitivity Interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei0 interrupts (Port A):
IS11 IS10 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
USB mode (48 MHz PLL)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU output on I/O port) Bits 4:3 = IS2[1:0] ei1 Interrupt sensitivity Interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the ei1 external interrupts (Port D):
IS21 IS20 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
Caution: - The ST7 core is not able to read or write in the USB data buffer if the ST7265x is configured at 6 MHz in standalone mode. - In USB mode, with fCPU 2 MHz, if the ST7 core accesses the USB data buffer, this may prevent the USB interface from accessing the buffer, resulting in a USB buffer overrun error. This is because an access to memory lasts one cycle and the USB has to send/receive at a fixed baud rate. Bit 0 = CPEN Clock Prescaler Enable This bit is set and cleared by software. It is used with the CP[1:0] bits to configure the internal clock frequency. 0: Default fCPU used (3 or 6 MHz) 1: fCPU determined by CP[1:0] bits
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).
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MISCELLANEOUS REGISTERS (Cont'd) MISCELLANEOUS REGISTER 2 (MISCR2) Reset Value: 0000 0000 (00h)
7 0 0 0 P4 P3 P2 P1 0 P0
Bits 7:5 = Reserved. Bits 4:0 = P[4:0] Power Management Bits These bits are set and cleared by software. They can be used to switch the on-chip peripherals of the microcontroller ON or OFF. The registers are not changed by switching the peripheral OFF and then ON (contents are frozen while OFF). 0: Peripheral ON (running) 1: Peripheral OFF
Bit P0 P1 P2 P3 P4 Peripheral PWM Timer I2C USB DTC
In either case, the Watchdog will not reset the MCU if a HALT instruction is executed while the USB is in Suspend mode. 0: If the Watchdog is active, it will reset the MCU if a HALT instruction is executed (unless the USB is in Suspend mode) 1: When a HALT instruction is executed, the MCU will enter Halt mode (without generating a reset) even if the Watchdog is active. Bits 6:4 = Reserved, forced by hardware to 0. Bits 3:2= IS3[1:0] ei2 Interrupt sensitivity Interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei2 interrupts (Port C):
IS31 IS30 0 0 0 1 1 0 1 1 External Interrupt Sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge
These 2 bits must be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 1 = PWM1 PWM1 Output Control 0: PWM1 Output alternate function disabled (I/O pin free for general purpose I/O). 1: PWM1 Output alternate function enabled
0
MISCELLANEOUS REGISTER 3 (MISCR3) Read /Write Reset Value: 0000 0000 (00h)
7 WDG HALT 0 0 0 IS31
IS30 PWM1 PWM0
Bit 7 = WDGHALT Watchdog and HALT Mode This bit is set and cleared by software. It determines if a RESET is generated when entering Halt mode while the Watchdog is active (WDGA bit =1 in the WDGCR register).
Bit 0 = PWM0 PWM0 Output Control 0: Output alternate function disabled (I/O pin free for general purpose I/O). 1: PWM0 Output alternate function enabled
Table 16. Miscellaneous Register Map and Reset Values
Address (Hex.) 49 4A 4C Register Label MISCR1 Reset Value MISCR2 Reset Value MISCR3 Reset Value 7 IS11 0 0 0 WDGHALT 0 6 IS10 0 0 0 0 0 5 MCO 0 0 0 0 0 4 IS21 0 P4 0 0 0 3 IS20 0 P3 0 IS31 0 2 CP1 0 P2 0 IS30 0 1 CP0 0 P1 0 PWM1 0 0 CPEN 0 P0 0 PWM0 0
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11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before the T6 bit becomes cleared. 11.1.2 Main Features s Programmable free-running downcounter (64 increments of 65536 CPU cycles) s Programmable reset s Reset (if watchdog activated) when the T6 bit reaches zero s Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]), is decremented every 65,536 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. Figure 37. Watchdog Block Diagram
RESET
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is freerunning: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 17): - The WDGA bit is set (watchdog enabled) - The T6 bit is set to prevent generating an immediate reset - The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 17.Watchdog Timing (fCPU = 8 MHz)
CR Register initial value Max Min FFh C0h WDG timeout period (ms) 524.288 8.192
WATCHDOG CONTROL REGISTER (CR) WDGA T6 T5 T4 T3 T2 T1 T0
7-BIT DOWNCOUNTER
fCPU
CLOCK DIVIDER /65536
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WATCHDOG TIMER (Cont'd) 11.1.4 Software Watchdog Option If Software Watchdog is selected by option byte, the watchdog is disabled following a reset. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 11.1.6 Low Power Modes
Mode WAIT
11.1.5 Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.
Description
HALT
No effect on Watchdog. If the WDGHALT bit in the MISCR3 register is set, Halt mode can be used when the watchdog is enabled. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 514 CPU clocks. In the case of the Software Watchdog option, if a reset is generated, the WDG is disabled (reset state). Note: In USB mode, and in Suspend mode, a reset is not generated by entering Halt mode
Recommendations - Make sure that an external event is available to wake up the microcontroller from Halt mode. - Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. - When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as Input before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. 11.1.7 Interrupts None.
- The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E. - As the HALT instruction clears the I bits in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).
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WATCHDOG TIMER (Cont'd) 11.1.8 Register Description CONTROL REGISTER (CR) Read /Write Reset Value: 0111 1111 (7Fh)
7 WDGA T6 T5 T4 T3 T2 T1 0 T0
hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by
Table 18. Watchdog Timer Register Map and Reset Values
Address (Hex.) 14 Register Label WDGCR Reset Value 7 WDGA 0 6 T6 1 5 T5 1 4 T4 1 3 T3 1 2 T2 1 1 T1 1 0 T0 1
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11.2 DATA TRANSFER COPROCESSOR (DTC) 11.2.1 Introduction The Data Transfer Coprocessor is a Universal Serial/Parallel Communications Interface. By means of software plug-ins provided by STMicroelectronics, the user can configure the ST7 to handle a wide range of protocols and physical interfaces such as: - 8 or 16-bit IDE mode Compact Flash - Multimedia Card (MMC protocol) - SmartMediaCard - Secure Digital Card Support for different devices or future protocol standards does not require changing the microcontroller hardware, but only installing a different software plug-in. Once the plug-in (up to 256 bytes) stored in the ROM or FLASH memory of the ST7 device is loaded in the DTC RAM, and that the DTC operation is Figure 38. DTC Block Diagram
ST7 DATA/ADDRESS BUS
started, the I/O ports mapped to the DTC assume specific alternate functions. Main Features s Full-Speed data transfer from USB to I/O ports without ST7 core intervention s Protocol-independency s Support for serial and parallel devices s Maskable Interrupts 11.2.2 Functional Description The block diagram is shown in Figure 38. The main function of the DTC is to quickly transfer data between : s USB and ST7 I/O ports s in between ST7 I/O ports The protocol used to read or write from the I/O port is defined by the S/W plug-in in the DTC RAM.
DTCPR MSB LSB
I/O PORTS
DATA TRANSFER COPROCESSOR
DATA TRANSFER BUFFER
TO USB INTERFACE
DTC RAM DTCCR 0 0 0
ERR STOP EN EN LOAD INIT RUN
DTCSR 0 0 0 0 0 0
ERRORSTOP
INTERRUPT REQUEST
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Data Transfer Coprocessor (Cont'd) When the USB interface is used, data transfer is typically controlled by a host computer. The ST7 core can also read from and write to the data buffer of the DTC. Typically, the ST7 controls the application when the USB not used (autonomous mode). The buffer can potentially be accessed by any one of three requestors, the ST7, the DTC and the USB. Mastership of the buffer is not time limited. While a master is accessing the buffer, other requests will not be acknowleged until the buffer is freed by the master. If several requests are pending, when the buffer is free it is granted to the source with the highest priority in the daisy-chain (fixed by hardware), first the ST7, secondly the USB and finally the DTC. Note: Any access by the ST7 to the buffer requires more cycles than either a DTC or USB access. For performance reasons, when the USB interface is exchanging data with the DTC, ST7 accesses should be avoided if possible. 11.2.3 Loading the Protocol Software The DTC must first be initialized by loading the protocol-specific software plug-in (provided by STMicroelectronics) into the DTC RAM. To do this: 1. Stop the DTC by clearing the RUN bit in the DTCCR register 2. Remove the write protection by setting the LOAD bit in the DTCCR register 3. Load the (null-terminated) software plug-in in the DTC RAM. Figure 39. State Diagram of DTC Operations
RUN=0 INIT=0 LOAD=1
4. Restore the write protection by clearing the LOAD bit in the DTCCR register The DTC is then ready for operation. 11.2.4 Executing the Protocol Functions To execute any of the software plug-in functions follow the procedure below: 1. Clear the RUN bit to stop the DTC 2. Select the function by writing its address in the DTCPR register (refer to the separate document for address information). 3. Set the INIT bit in the DTCCR register to copy the DTCPR pointer to the DTC. 4. Clear the INIT bit to return to idle state. 5. Set the RUN bit to start the DTC. 11.2.5 Changing the DTCPR pointer on the fly As shown in Figure 39, the pointer can be changed by writing INIT=1 while the DTC is running (RUN=1), however if the DTC is executing an internal interrupt routine, there will be a delay until interrupt handling is completed. 11.2.6 Low Power Modes Mode WAIT HALT Description No effect on DTC DTC halted.
DTC RAM LOAD
LOAD=0
RUN=0 INIT=0 LOAD=0
RUN=1 INIT=0 LOAD=0 RUN=0
LOAD=1 INIT=1
DTC IDLE
DTC RUNNING
RUN=1 INIT=0 INIT=1
INIT=0
POINTER CHANGE
RUN=0 INIT=1 LOAD=0
ON-THE-FLY POINTER CHANGE
RUN=1 INIT=1 LOAD=0
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Data Transfer Coprocessor (Cont'd) 11.2.7 Interrupts
Interrupt Event Error Stop Enable Control Bit ERROR ERREN STOP STOPEN Event Flag Exit from Wait Yes Yes Exit from Halt No No
Bit 0 = RUN START/STOP Control This bit is set and cleared by software. It can only be set while LOAD=0. It is also cleared by hardware when STOP=1 0: Stop DTC 1: Start DTC DTC STATUS REGISTER (DTCSR) Read/Write Reset Value: 0000 0000 (00h)
7
0 0 0 0 0 0 ERROR
Note: The DTC interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). 11.2.8 Register Description DTC CONTROL REGISTER (DTCCR) Read/Write Reset Value: 0000 0000 (00h)
7
0 0 0 ERR EN STOP EN LOAD INIT
0
STOP
Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1 = ERROR Error Flag This bit is set by hardware and cleared by software reading this register. 0: No Error event occurred 1: Error event occurred (DTC is running) Bit 0 = STOP Stop Flag This bit is set by hardware and cleared by software reading this register. 0: No Stop event occurred 1: Stop event occurred (DTC terminated execution at the current intruction) DTC POINTER REGISTER (DTCPR) Write Only Reset Value: 0000 0000 (00h)
7
MSB
0
RUN
Bit 7:5 = Reserved. Must be left at reset value. Bit 4 = ERREN Error Interrupt Enable This bit is set and cleared by software. 0: Error interrupt disabled 1: Error interrupt enabled Bit 3 = STOPEN Stop Interrupt Enable This bit is set and cleared by software. 0: Stop interrupt disabled 1: Stop interrupt enabled Bit 2 = LOAD Load Enable This bit is set and cleared by software. It can only be set while RUN=0. 0: Write access to DTC RAM disabled 1: Write access DTC RAM enabled Bit 1 = INIT Initialization This bit is set and cleared by software. 0: Do not copy DTCPR to DTC 1: Copy the DTCPR pointer to DTC
0
LSB
Bit 7:0 = PC[7:0] Pointer Register. This register is written by software. It gives the address of an entry point in the protocol software that has previously been loaded in the DTC RAM. Note: To start executing the function, after writing this address, set the INIT bit.
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11.2.8.1 Data Transfer Coprocessor (Cont'd) Table 19. DTC Register Map and Reset Values
Address (Hex.) Register Label 7 6 5 4 3 2 1 0
1C
DTCCR
0 0 0 0 MSB 0
0 0 0 0
0 0 0 0
ERREN 0 0 0
STOPEN 0 0 0
LOAD 0 0 0
INIT 0 ERROR 0
RUN 0 STOP 0 LSB 0
1D
DTCSR
1F
DTCPR
0
0
0
0
0
0
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11.3 USB INTERFACE (USB) 11.3.1 Introduction The USB Interface implements a full-speed function interface between the USB and the ST7 microcontroller. It is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, SIE and USB Data Buffer interface. No external components are needed apart from the external pullup on USBDP for full speed recognition by the USB host. 11.3.2 Main Features s USB Specification Version 2.0 Compliant s Supports Full-Speed USB Protocol s Five Endpoints (including default endpoint) s CRC generation/checking, NRZI encoding/ decoding and bit-stuffing s USB Suspend/Resume operations s Special Data transfer mode with USB Data Buffer Memory (2 x 512 bytes for upload or download) to DTC s On-Chip 3.3V Regulator s On-Chip USB Transceiver 11.3.3 Functional Description The block diagram in Figure 40, gives an overview of the USB interface hardware. Figure 40. USB Block Diagram 48 MHz For general information on the USB, refer to the "Universal Serial Bus Specifications" document available at http//:www.usb.org. Serial Interface Engine The SIE (Serial Interface Engine) interfaces with the USB, via the transceiver. The SIE processes tokens, handles data transmission/reception, and handshaking as required by the USB standard. It also performs frame formatting, including CRC generation and checking. Endpoints The Endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. Data Transfer to/from USB Data Buffer Memory When a token for a valid Endpoint is recognized by the USB interface, the related data transfer takes place to/from the USB data buffer. In normal configuration (MOD[1:0] bits=00 in the CTLR register), at the end of the transaction, an interrupt is generated. Interrupts By reading the Interrupt Status register, application software can know which USB event has occurred.
ENDPOINT REGISTERS CPU
USBDM USBDP
Transceiver
BUFFER SIE INTERFACE
Address, data busses and interrupts
USBVCC
3.3V Voltage Regulator
USB REGISTERS
USB DATA BUFFER
USBGND
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USB INTERFACE (Cont'd) USB Endpoint RAM Buffers There are five bidirectional Endpoints including one control Endpoint 0. Endpoint 1 and Endpoint 2 are counted as 4 bulk or interrupt Endpoints (two IN and two OUT). Endpoint 0 and Endpoint 1 are both 2 x 16 bytes in size. Endpoint 2 is 2 x 64 bytes in size and can be configured to physically target different USB Data Buffer areas depending on the MOD[1:0] bits in
the CTLR register (see Figure 41, Figure 42 and Figure 43). The USB Data Buffer operates as a double buffer; while one 512-byte block is being read/written by the DTC, the USB interface reads/writes the other 512-byte block. The management of the data transfer is performed in upload and download mode (2 x 512 byte buffers for Endpoint 2) by the USB Data Buffer Manager.
Figure 41. Endpoint 2 Normal Mode selected by (MOD[1:0] Bits = 00h) 1550h 155Fh 156Fh 157Fh 158Fh
Endpoint 0 Buffer OUT Endpoint 0 Buffer IN Endpoint 1 Buffer OUT Endpoint 1 Buffer IN Endpoint 2 Buffer OUT
16 Bytes 16 Bytes 16 Bytes 16 Bytes 64 Bytes
15CFh Endpoint 2 Buffer IN 160Fh Figure 42. Endpoint 2 Download Mode selected by MOD[1:0] Bits = 10b
1550h 1590h 15CFh 1650h
64 Bytes
Endpoint 0 Buffer OUT Endpoint 0 Buffer IN Endpoint 1 Buffer OUT
USB DATA USB DATA USB DATA
64-byte buffer
158Fh
Endpoint 1 Buffer IN Endpoint 2 Buffer IN Endpoint 2 Buffer OUT USB DATA USB DATA
512-byte buffer as 64-byte slices
512-byte buffer as 64-byte slices 1A4Fh
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USB INTERFACE (Cont'd) Figure 43. Endpoint 2 Upload Mode selected by MOD[1:0] Bits = 01b
1550h Endpoint 0 Buffer OUT Endpoint 0 Buffer IN Endpoint 1 Buffer OUT 158Fh Endpoint 1 Buffer IN Endpoint 2 Buffer OUT Endpoint 2 Buffer IN USB DATA USB DATA 512-byte buffer as 64-byte slices 1A4Fh 1590h 15CFh 1650h USB DATA USB DATA USB DATA 512-byte buffer as 64-byte slices 64-byte buffer
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USB INTERFACE (Cont'd) 11.3.4 USB Data Buffer Manager The USB Data Buffer Manager performs the data transfer between the USB interface and the two 512 Bytes RAM areas used for Endpoint 2 in both Upload and Download modes. It also controls the status of Endpoint 2, by setting the endpoint as NAK when the current buffer is not yet available for either transmission (Upload) or reception (Download). It is based on a stand-alone hardware state-machine that runs in parallel to the ST7 processing flow. However, at any time, the ST7 software can initialize the USB Data Buffer Manager state-machine in order to synchronize operations by writing a `1' to the CLR bit in the BUFCSR register. Dedicated buffer status flags are defined to synchronize the USB Data Buffer Manager with the Data Transfer Coprocessor (DTC). These flags are used by the software plug-ins provided by STMicroelectronics) running on the DTC. 11.3.4.1 Data Transfer Modes In USB normal mode (MOD[1:0]=00b), the maximum memory size of Endpoint 2 is 64 bytes, and therefore reception of 512 bytes packets requires ST7 software intervention every 64 bytes. This means that after a CTR interrupt the hardware puts the Endpoint 2 status bits for the current direction (transmit or receive) in NAK status. The
ST7 software must then write the status bits to VALID when it is ready to transmit or receive new data. On the contrary, in Upload or Download mode, the physical address of Endpoint 2 is automatically incremented every 64 bytes until a 512-byte buffer is full. Toggling between the two buffers is automatically managed as soon as 512 bytes have been transmitted to USB (Upload mode) or received from USB (Download), if the next buffer is available: Otherwise, the endpoint is set to invalid until a buffer has been released by the DTC. 11.3.4.2 Switching back to Normal Mode The USB interface is reset by hardware in Normal mode on reception of a packet with a length below the maximum packet size. In this case, the few bytes are received into one of the two 512-byte buffers and the ST7 must process by software the data received. For this purpose, the information indicating which 512-byte buffer was last addressed is given to the ST7 by the USB Data Buffer Manager (BUFNUM bit in the BUFCSR register), and the number of received bytes is obtained by reading the USB interface registers. With these two items of information, the ST7 can determine what kind of data has been received, and what action has to be taken.
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USB INTERFACE (Cont'd) Figure 44. Overview of USB, DTC and ST7 Interconnections USB SIE
CLR
BUFCSR Register (19h)
0
0
0
0
BUF STAT STAT B0 NUM B1
DATA TRANSFER BUFFER (1280 bytes)
1550h
USB DATA BUFFER MANAGER
1650h
USB EP0 USB EP1 USB EP2 Parameters
BUFFER ACCESS ARBITRATION
512-byte RAM Buffer 512-byte RAM Buffer
1850h
1A4Fh
DATA TRANSFER COPROCESSOR (DTC)
DTC I/Os (EXTERNAL DEVICES)
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USB INTERFACE (Cont'd) 11.3.5 Low Power modes
Mode WAIT No effect on USB. USB interrupt events cause the device to exit from WAIT mode. USB registers are frozen. In halt mode, the USB is inactive. USB operations resume when the MCU is woken up by an interrupt with "exit from halt capability" or by an event on the USB line in case of suspend. This event will generate an ESUSP interrupt which will wake-up from halt mode. Description
HALT
11.3.6 Interrupts
Interrupt Event Correct TRansfer Setup OVeRrun ERROR Suspend Mode Request End of SUSPend mode. USB RESET Start Of Frame Event Flag CTR SOVR ERR SUSP ESUSP RESET SOF Enable Con- Exit From trol Bit Wait CTRM SOVRM ERRM SUSPM ESUSPM RESETM SOFM Yes Yes Yes Yes Yes Yes Yes Exit From Halt No No No No Yes No No
Note: The USB end of suspend interrupt event is connected to a single interrupt vector (USB ESUSP) with the exit from halt capability (wake-up). All the other interrupt events are connected to another interrupt vector: USB interrupt (USB). They generate an interrupt if the corresponding enable control bit is set and the interrupt mask bits (I0, I1) in CC register are reset (RIM instruction).
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USB INTERFACE (Cont'd) 11.3.7 Register Description BUFFER CONTROL/STATUS (BUFCSR) Read Only (except bit 0, read/write) Reset Value: 0000 0000 (00h)
7 0 0 0 0 BUFNUM STAT B1
REGISTER
INTERRUPT STATUS REGISTER (ISTR) Read/Write Reset Value: 0000 0000 (00h)
7 0 0 SOVR ERROR SUSP ESUSP RESET SOF
0 STAT B0 CLR
CTR
Bits 7:4 = Reserved, forced by hardware to 0. Bit 3 = BUFNUM Current USB Buffer Number This bit is set and cleared by hardware. When data are received by Endpoint 2 in normal mode (refer to the description of the MOD[1:0] bits in the EP2RXR register) it indicates which buffer contains the data. 0: Current buffer is Buffer 0 1: Current buffer is Buffer 1 Bits 2:1 = STATB[1:0] Buffer Status Bits These bits are set and cleared by hardware. When data are transmitted or received by Endpoint 2 in upload or download mode (refer to the description of the MOD[1:0] bits in the EP2RXR register) the STATB[1:0] bits indicate the status as follows:
Meaning Buffer n not full (USB waiting to Upload read Buffer n) Mode Buffer n full (USB can upload this buffer) Buffer n empty (Can be written to Download by USB) Mode Buffer n not empty (USB waiting to write to this buffer) STATBn Value 0 1 0 1
These bits cannot be set by software. When an interrupt occurs these bits are set by hardware. Software must read them to determine the interrupt type and clear them after servicing. Note: The CTR bit (which is an OR of all the endpoint CTR flags) cannot be cleared directly, only by clearing the CTR flags in the Endpoint registers. Bit 7 = CTR Correct Transfer. This bit is set by hardware when a correct transfer operation is performed. This bit is an OR of all CTR flags (CTR0 in the EP0R register and CTR_RX and CTR_TX in the EPnR registers). By looking in the USBSR register, the type of transfer can be determined from the PID[1:0] bits for Endpoint 0. For the other Endpoints, the Endpoint number on which the transfer was made is identified by the EP[1:0] bits and the type of transfer by the IN/OUT bit. 0: No Correct Transfer detected 1: Correct Transfer detected Note: A transfer where the device sent a NAK or STALL handshake is considered not correct (the host only sends ACK handshakes). A transfer is considered correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1 PID is sent as expected, if there were no data overruns, bit stuffing or framing errors. Bit 6 = Reserved, forced by hardware to 0. Bit 5 = SOVR Setup Overrun. This bit is set by hardware when a correct Setup transfer operation is performed while the software is servicing an interrupt which occurred on the same Endpoint (CTR0 bit in the EP0R register is still set when SETUP correct transfer occurs). 0: No SETUP overrun detected 1: SETUP overrun detected When this event occurs, the USBSR register is not updated because the only source of the SOVR event is the SETUP token reception on the Control Endpoint (EP0).
Bit 0 = CLR Clear Buffer Status This bit is written by software to clear the BUFNUM and STATB[1:0] bits (it also resets the packet counter of the Buffer Manager state machine). It can be used to re-initialize the upload/download flow (refer to the description of the MOD[1:0] bits in the EP2RXR register). 0: No effect 1: Clear BUFNUM and STATB[1:0] bits
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USB INTERFACE (Cont'd) Bit 4 = ERR Error. This bit is set by hardware whenever one of the errors listed below has occurred: 0: No error detected 1: Timeout, CRC, bit stuffing, nonstandard framing or buffer overrun error detected Note: Refer to the ERR[2:0] bits in the USBSR register to determine the error type. Bit 3 = SUSP Suspend mode request. This bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the USB. The suspend request check is active immediately after each USB reset event and is disabled by hardware when suspend mode is forced (FSUSP bit in the CTLR register) until the end of resume sequence. Bit 2 = ESUSP End Suspend mode. This bit is set by hardware when, during suspend mode, activity is detected that wakes the USB interface up from suspend mode. This interrupt is serviced by a specific vector, in order to wake up the ST7 from HALT mode. 0: No End Suspend detected 1: End Suspend detected Bit 1 = RESET USB reset. This bit is set by hardware when the USB reset sequence is detected on the bus. 0: No USB reset signal detected 1: USB reset signal detected Note: The DADDR, EP0R, EP1RXR, EP1TXR and EP2RXR, EP2TXR registers are reset by a USB reset. Bit 0 = SOF Start of frame. This bit is set by hardware when a SOF token is received on the USB. 0: No SOF received 1: SOF received Note: To avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. Avoid readmodify-write instructions like AND, XOR..
INTERRUPT MASK REGISTER (IMR) Read/Write Reset Value: 0000 0000 (00h)
7 CTRM 0 0 SOVR SUSP ESUSP RESET ERRM SOFM M M M M
These bits are mask bits for all the interrupt condition bits included in the ISTR register. Whenever one of the IMR bits is set, if the corresponding ISTR bit is set, and the I- bit in the CC register is cleared, an interrupt request is generated. For an explanation of each bit, please refer to the description of the ISTR register. CONTROL REGISTER (CTLR) Read/Write Reset value: 0000 0110 (06h)
7 USB_ RST RESU PDWN FSUSP ME 0
RSM
0
0
FRES
Bit 7 = RSM Resume Detected This bit shows when a resume sequence has started on the USB port, requesting the USB interface to wake-up from suspend state. It can be used to determine the cause of an ESUSP event. 0: No resume sequence detected on USB 1: Resume sequence detected on USB Bit 6 = USB_RST USB Reset detected. This bit shows that a reset sequence has started on the USB. It can be used to determine the cause of an ESUSP event (Reset sequence). 0: No reset sequence detected on USB 1: Reset sequence detected on USB Bits 5:4 Reserved, forced by hardware to 0. Bit 3 = RESUME Resume. This bit is set by software to wake-up the Host when the ST7 is in suspend mode. 0: Resume signal not forced 1: Resume signal forced on the USB bus. Software should clear this bit after the appropriate delay.
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USB INTERFACE (Cont'd) Bit 2 = PDWN Power down. This bit is set by software to turn off the 3.3V onchip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: Voltage regulator on 1: Voltage regulator off Note: After turning on the voltage regulator, software should allow at least 3 s for stabilisation of the power supply before using the USB interface. Bit 1 = FSUSP Force suspend mode. This bit is set by software to enter Suspend mode. The ST7 should also be put in Halt mode to reduce power consumption. 0: Suspend mode inactive 1: Suspend mode active When the hardware detects USB activity, it resets this bit (it can also be reset by software). Bit 0 = FRES Force reset. This bit is set by software to force a reset of the USB interface, just as if a RESET sequence came from the USB. 0: Reset not forced 1: USB interface reset forced. The USB interface is held in RESET state until software clears this bit, at which point a "USB-RESET" interrupt will be generated if enabled. DEVICE ADDRESS REGISTER (DADDR) Read/Write Reset Value: 0000 0000 (00h)
7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 ADD0
Note: This register is also reset when a USB reset is received or forced through bit FRES in the CTLR register. USB STATUS REGISTER (USBSR) Read only Reset Value: 0000 0000 (00h)
7 IN/ OUT 0
PID1
PID0
EP1
EP0
ERR2
ERR1
ERR0
Bits 7:6 = PID[1:0] Token PID bits 1 & 0 for Endpoint 0 Control. USB token PIDs are encoded in four bits. PID[1:0] correspond to the most significant bits of the PID field of the last token PID received by Endpoint 0. Note: The least significant PID bits have a fixed value of 01. When a CTR interrupt occurs on Endpoint 0 (see register ISTR) the software should read the PID[1:0] bits to retrieve the PID name of the token received. The USB specification defines PID bits as:
PID1 0 1 1 PID0 0 0 1 PID Name OUT IN SETUP
Bit 5 = IN/OUT Last transaction direction for Endpoint 1 or 2. This bit is set by hardware when a CTR interrupt occurs on Endpoint 1 or Endpoint 2. 0: OUT transaction 1: IN transaction Bits 4:3 = EP[1:0] Endpoint number. These bits identify the endpoint which required attention. 00 = Endpoint 0 01 = Endpoint 1 10 = Endpoint 2
Bit 7 Reserved, forced by hardware to 0. Bits 6:0 = ADD[6:0] Device address, 7 bits. Software must write into this register the address sent by the host during enumeration.
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USB INTERFACE (Cont'd) Bits 2:0 = ERR[2:0] Error type. These bits identify the type of error which occurred:
ERR2 ERR1 ERR0 Meaning 0 0 0 No error 0 0 1 Bitstuffing error 0 1 0 CRC error EOP error (unexpected end of 0 1 1 packet or SE0 not followed by J-state) PID error (PID encoding error, 1 0 0 unexpected or unknown PID) Memory over / underrun (memory controller has not an1 0 1 swered in time to a memory data request) Other error (wrong packet, 1 1 1 timeout error)
data packet. This bit is set by hardware on reception of a SETUP PID. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and also DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits 5:4 = STAT_TX [1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, as listed below: Table 20. Transmission Status Encoding
STAT_TX1 STAT_TX0 0 0 Meaning DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is NAKed and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).
Note: These bits are set by hardware when an error interrupt occurs and are reset automatically when the error bit (ISTR bit 4) is cleared by software. ENDPOINT 0 REGISTER (EP0R) Read/Write Reset value: 0000 0000 (00h)
7 DTOG STAT_ STAT_ _TX TX1 TX0 0 DTOG STAT_ STAT_ _RX RX1 RX0
0
1
1
0
1
1
CTR0
0
This register is used for controlling Endpoint 0. Bits 6:4 and bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in CTLR. Bit 7 = CTR0 Correct Transfer. This bit is set by hardware when a correct transfer operation is performed on Endpoint 0. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR on Endpoint 0 1: Correct transfer on Endpoint 0 Bit 6 = DTOG_TX Data Toggle, for transmission transfers. It contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next transmitted
These bits are written by software. Hardware sets the STAT_TX and STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint; this allows software to prepare the next set of data to be transmitted. Bit 3 = Reserved, forced by hardware to 0. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. This bit is cleared by hardware in the first stage (Setup Stage) of a control transfer (SETUP transactions start always with DATA0 PID). The receiver toggles DTOG_RX only if it receives a correct data packet and the packet's data PID matches the receiver sequence bit.
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USB INTERFACE (Cont'd) Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, as listed below: Table 21. Reception Status Encoding
STAT_RX1 STAT_RX0 0 0 Meaning DISABLED: no function can be executed on this endpoint and messages related to this endpoint are ignored. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is NAKed and all reception requests result in a NAK handshake. VALID: this endpoint is enabled (if an address match occurs, the USB interface handles the transaction).
This register is used for controlling Endpoint 1 reception. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register. Bits 7:4 Reserved, forced by hardware to 0. Bit 3 = CTR_RX Correct Reception Transfer. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after the corresponding interrupt has been serviced. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. The receiver toggles DTOG_RX only if it receives a correct data packet and the packet's data PID matches the receiver sequence bit. Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, as listed below: Table 22. Reception Status Encoding:
STAT_RX1 STAT_RX0 0 0 0 1 Meaning DISABLED: reception transfers cannot be executed. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception.
0
1
1
0
1
1
These bits are written by software. Hardware sets the STAT_RX and STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. Notes: If a SETUP is received while the status is other than DISABLED, it is acknowledged and the two directional status bits are set to NAK by hardware. When a STALL is answered by the USB device, the two directional status bits are set to STALL by hardware. ENDPOINT 1 RECEPTION (EP1RXR) Read/Write Reset value: 0000 0000 (00h)
7
1
0 1
REGISTER
1
0 CTR_R DTOG STAT_ STAT_ X _RX RX1 RX0
0
0
0
0
These bits are written by software, but hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction.
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USB INTERFACE (Cont'd) ENDPOINT 1 TRANSMISSION (EP1TXR) Read/Write Reset value: 0000 0000 (00h)
7
REGISTER
These bits are written by software, but hardware sets the STAT_TX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint. This allows software to prepare the next set of data to be transmitted.
0 CTR_T DTOG STAT_ STAT_ X _TX TX1 TX0
0
0
0
0
This register is used for controlling Endpoint 1 transmission. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register. Bit 3 = CTR_TX Correct Transmission Transfer. This bit is set by hardware when a correct transfer operation is performed in transmission. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR in transmission on Endpoint 1 1: Correct transfer in transmission on Endpoint 1 Bit 2 = DTOG_TX Data Toggle, for transmission transfers. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX toggles only when the transmitter has received the ACK signal from the USB host. DTOG_TX and DTOG_RX are normally updated by hardware, at the receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits 1:0 = STAT_TX [1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which is listed below Table 23. Transmission Status Encoding
STAT_TX1 STAT_TX0 0 0 0 1 Meaning DISABLED: transmission transfers cannot be executed. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled for transmission.
ENDPOINT 2 RECEPTION (EP2RXR) Read/Write Reset value: 0000 0000 (00h)
7
REGISTER
0 CTR_R DTOG STAT_ STAT_ X _RX RX1 RX0
MOD1 MOD0
0
0
This register is used for controlling endpoint 2 reception. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register. Bits 7:6 = MOD[1:0] Endpoint 2 mode. These bits are set and cleared by software. They select the Endpoint 2 mode (See Figure 42 and Figure 43).
MOD1 MOD0 0 0 0 1 Mode Normal mode: Endpoint 2 is managed by user software Upload mode to USB data buffer: Bulk mode IN under hardware control from DTC1 Download mode from USB data buffer: Bulk mode OUT under hardware control to DTC2.
1
0
Notes: 1. Before selecting Download mode, software must write the maximum packet size value (for instance 64) in the CNT2RXR register and write the STAT_RX bits in the EP2RXR register to VALID. 2. Before selecting Upload mode, software must write the maximum packet size value (for instance 64) in the CNT2TXR register and write the STAT_TX bits in the EP2TXR register to NAK.
1 1
0 1
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USB INTERFACE (Cont'd) Download Mode IN transactions are managed the same way as in normal mode (by software with the help of CTR interrupt) but OUT transactions are managed by hardware. This means that no CTR interrupt is generated at the end of an OUT transaction and the STAT_RX bits are set to valid by hardware when the buffer is ready to receive new data. This allows the 512-byte buffer to be written without software intervention. If the USB interface receives a packet which has a length lower than the maximum packet size (written in the CNT2RXR register, see Note below), the USB interface switches back to normal mode and generates a CTR interrupt and the STAT_RX bits of the EP2R register are set to NAK by hardware as in normal mode. Upload Mode OUT transactions are managed in the same way as normal mode and IN transactions are managed by hardware in the same way as OUT transactions in download mode. Bits 5:4 Reserved, forced by hardware to 0. Bit 3 = CTR_RX Reception Correct Transfer. This bit is set by hardware when a correct transfer operation is performed in reception. This bit must be cleared after that the corresponding interrupt has been serviced. Bit 2 = DTOG_RX Data Toggle, for reception transfers. It contains the expected value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. USB INTERFACE (Cont'd) The receiver toggles DTOG_RX only if it receives a correct data packet and the packet's data PID matches the receiver sequence bit. Bits 1:0 = STAT_RX [1:0] Status bits, for reception transfers. These bits contain the information about the endpoint status, which is listed below:
Table 24. Reception Status Encoding
STAT_RX1 STAT_RX0 0 0 0 1 Meaning DISABLED: reception transfers cannot be executed. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception.
1 1
0 1
These bits are written by software, but hardware sets the STAT_RX bits to NAK when a correct transfer has occurred (CTR=1) addressed to this endpoint, so the software has the time to examine the received data before acknowledging a new transaction. Note: These bits are write protected in download mode (if MOD[1:0] =10b in the EP2RXR register) ENDPOINT 2 TRANSMISSION (EP2TXR) Read/Write Reset value: 0000 0000 (00h)
7
REGISTER
0 CTR_T DTOG STAT_ STAT_ X _TX TX1 TX0
0
0
0
0
This register is used for controlling Endpoint 2 transmission. Bits 2:0 are also reset by a USB reset, either received from the USB or forced through the FRES bit in the CTLR register. Bit 3 = CTR_TX Transmission Transfer Correct. This bit is set by hardware when a correct transfer operation is performed in transmission. This bit must be cleared after the corresponding interrupt has been serviced. 0: No CTR in transmission on Endpoint 2 1: Correct transfer in transmission on Endpoint 2
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USB INTERFACE (Cont'd) Bit 2= DTOG_TX Data Toggle, for transmission transfers. This bit contains the required value of the toggle bit (0=DATA0, 1=DATA1) for the next data packet. DTOG_TX and DTOG_RX are normally updated by hardware, on receipt of a relevant PID. They can be also written by the user, both for testing purposes and to force a specific (DATA0 or DATA1) token. Bits 1:0 = STAT_TX [1:0] Status bits, for transmission transfers. These bits contain the information about the endpoint status, which is listed below Table 25. Transmission Status Encoding
STAT_TX1 STAT_TX0 0 0 0 1 Meaning DISABLED: transmission transfers cannot be executed. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled for transmission.
number of bytes received, the software must subtract the content of this register from the allocated buffer size). RECEPTION COUNTER REGISTER (CNT2RXR) Read/Write Reset Value: 0000 0000 (00h)
7 0
0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0
1 1
0 1
This register contains the allocated buffer size for endpoint 2 reception, setting the maximum number of bytes the related endpoint can receive with the next OUT transaction. At the end of a reception, the value of this register is the maximum size decremented by the number of bytes received (to determine the number of bytes received, the software must subtract the content of this register from the allocated buffer size). TRANSMISSION COUNTER REGISTER (CNT0TXR, CNT1TXR) Read/Write Reset Value 0000 0000 (00h)
7 0
These bits are written by software, but hardware sets the STAT_TX bits to NAK when a correct transfer (CTR=1) addressed to this endpoint has occurred. This allows software to prepare the next set of data to be transmitted. Note: These bits are write protected in upload mode (MOD[1:0] =01b in the EP2RXR register) RECEPTION COUNTER REGISTER (CNT0RXR, CNT1RXR) Read/Write Reset Value: 0000 0000 (00h)
7 0
0
0
0
CNT4 CNT3 CNT2 CNT1 CNT0
This register contains the number of bytes to be transmitted by Endpoint 0 or 1 at the next IN token addressed to it. TRANSMISSION COUNTER REGISTER (CNT2TXR) Read/Write Reset Value 0000 0000 (00h)
7 0
0 0 0 0 CNT4 CNT3 CNT2 CNT1 CNT0
CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
This register contains the allocated buffer size for endpoint 0 or 1 reception, setting the maximum number of bytes the related endpoint can receive with the next OUT (or SETUP for Endpoint 0) transaction. At the end of a reception, the value of this register is the max size decremented by the number of bytes received (to determine the
This register contains the number of bytes to be transmitted by Endpoint 2 at the next IN token addressed to it.
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Table 26. USB Register Map and Reset values
Address (Hex.)
47
Register Name
BUFCSR Reset Value USBISTR Reset Value USBIMR Reset Value USBCTLR Reset Value DADDR Reset Value USBSR Reset Value EP0R Reset Value CNT0RXR Reset Value CNT0TXR Reset Value EP1RXR Reset Value CNT1RXR Reset Value EP1TXR Reset Value CNT1TXR Reset Value EP2RXR Reset Value CNT2RXR Reset Value EP2TXR Reset Value CNT2TXR Reset Value
7
0 0 CTR 0 CTRM 0 RSM 0 0 PID1 0 CTR0 0 0 0 0 0 0 0 0 0 0 0 MOD1 0 0 0 0 0 0
6
0 0 0 0 0 0 USB_RST 0 ADD6 0 PID0 0 DTOG_TX 0 0 0 0 0 0 0 0 0 0 0 MOD0 0 CNT6 0 0 CNT6 0
5
0 0 SOVR 0 SOVRM 0 0 ADD5 0 IN /OUT 0 STAT_TX1 0 0 0 0 0 0 0 0 0 0 0 0 CNT5 0 0 CNT5 0
4
0 0 ERR 0 ERRM 0 0 ADD4 0 EP1 0 STAT_TX0 0 CNT4 0 CNT4 0 0 CNT4 0 0 CNT4 0 0 CNT4 0 0 CNT4 0
3
BUFNUM 0 SUSP 0 SUSPM 0 RESUME 0 ADD3 0 EP0 0 0 0 CNT3 0 CNT3 0 CTR_RX 0 CNT3 0 CTR_TX 0 CNT3 0 CTR_RX 0 CNT3 0 CTR_TX 0 CNT3 0
2
BUF1ST 0 ESUSP 0 ESUSPM 0 PDWN 1 ADD2 0 ERR2 0 DTOG_RX 0 CNT2 0 CNT2 0 DTOG_RX 0 CNT2 0 DTOG_TX 0 CNT2 0 DTOG_RX 0 CNT2 0 DTOG_TX 0 CNT2 0
1
BUF0ST 0 RESET 0 RESETM 0 FSUSP 1 ADD1 0 ERR1 0 STAT_RX1 0 CNT1 0 CNT1 0 STAT_RX1 0 CNT1 0 STAT_TX1 0 CNT1 0 STAT_RX1 0 CNT1 0 STAT_TX1 0 CNT1 0
0
RESETST 0 SOF 0 SOFM 0 FRES 0 ADD0 0 ERR0 0 STAT_RX0 0 CNT0 0 CNT0 0 STAT_RX0 0 CNT0 0 STAT_TX0 0 CNT0 0 STAT_RX0 0 CNT0 0 STAT_TX0 0 CNT0 0
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
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11.4 16-BIT TIMER 11.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. 11.4.2 Main Features s Programmable prescaler: fCPU divided by 2, 4 or 8. s Overflow status flag and maskable interrupt s Output compare functions with - 2 dedicated 16-bit registers - 2 dedicated programmable signals - 2 dedicated status flags - 1 dedicated maskable interrupt s 2 alternate functions on I/O ports (OCMP1, OCMP2) The Block Diagram is shown in Figure 45. 11.4.3 Functional Description 11.4.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): - Counter High Register (CHR) is the most significant byte (MS Byte). - Counter Low Register (CLR) is the least significant byte (LS Byte). Alternate Counter Register (ACR) - Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). - Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 27 Clock Control Bits. The value in the counter register repeats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
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16-BIT TIMER (Cont'd) Figure 45. Timer Block Diagram
ST7 INTERNAL BUS fCPU MCU-PERIPHERAL INTERFACE
8 high
8 low
8-bit buffer
8 high low
8 high
8 low
8
EXEDG
16
1/2 1/4 1/8 COUNTER REGISTER ALTERNATE COUNTER REGISTER OUTPUT COMPARE REGISTER 1 OUTPUT COMPARE REGISTER 2
16
CC[1:0] TIMER INTERNAL BUS 16 16 OVERFLOW DETECT CIRCUIT
OUTPUT COMPARE CIRCUIT
6
LATCH1
0 OCF1 TOF 0 OCF2 0
OCMP1 pin OCMP2 pin
0 0
0
0 LATCH2
(Status Register) SR
0
OCIE TOIE FOLV2 FOLV1 OLVL2
0
OLVL1
OC1E OC2E
0
0
CC1
CC0
(Control Register 1) CR1
(Control Register 2) CR2
TIMER INTERRUPT
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16-BIT TIMER (Cont'd) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register).
Beginning of the sequence
At t0 Read MS Byte Other instructions Read At t0 +t LS Byte
Returns the buffered
LS Byte is buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read. Whatever the timer mode used an overflow occurs when the counter rolls over from FFFFh to 0000h then: - The TOF bit of the SR register is set.
- A timer interrupt is generated if: - TOIE bit of the CR1 register is set and - I bits of the CC register is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).
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16-BIT TIMER (Cont'd) Figure 46. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFD FFFE FFFF 0000 0001 0002 0003
Figure 47. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001
Figure 48. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
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16-BIT TIMER (Cont'd) 11.4.3.2 Output Compare In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Compare register and the free running counter, the output compare function: - Assigns pins with a programmable value if the OCIE bit is set - Sets a flag in the status register - Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OCiR MS Byte OCiHR LS Byte OCiLR
- The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). - A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bits are cleared in the CC register (CC). The OCiR register value required for a specific timing application can be calculated using the following formula:
OCiR =
Where:
t * fCPU
PRESC
t
= Output compare period (in seconds) = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 27 Clock Control Bits) fCPU If the timer clock is an external clock, the formula is:
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure: To use the output compare function, select the following in the CR2 register: - Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. - Select the timer clock (CC[1:0]) (see Table 27 Clock Control Bits). And select the following in the CR1 register: - Select the OLVLi bit to applied to the OCMPi pins after the match occurs. - Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: - OCFi bit is set.
OCiR = t * fEXT
Where:
t
fEXT
= Output compare period (in seconds) = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: - Write to the OCiHR register (further compares are inhibited). - Read the SR register (first step of the clearance of the OCFi bit, which may be already set). - Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
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16-BIT TIMER (Cont'd) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3. When the timer clock is fCPU/2, OCFi and OCMPi are set while the counter value equals the OCiR register value (see Figure 50 on page 86). When the timer clock is fCPU/4, fCPU/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure on page 86). 4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used. 5. The value in the 16-bit OCiR register and the OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new timeout period. Figure 49. Output Compare Block Diagram
Forced Compare Output capability When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.
16 BIT FREE RUNNING COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE CIRCUIT
(Control Register 2) CR2 (Control Register 1) CR1
OCIE FOLV2 FOLV1 OLVL2 OLVL1 Latch 1
OCMP1 Pin OCMP2 Pin
16-bit
16-bit
OC1R Register
OCF1 OCF2 0 0 0
Latch 2
OC2R Register (Status Register) SR
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16-BIT TIMER (Cont'd) Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/2
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
Figure 51. Output Compare Timing Diagram, fTIMER =fCPU/4
INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3
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16-BIT TIMER (Cont'd) 11.4.4 Low Power Modes
Mode WAIT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter reset value when the MCU is woken up by a RESET.
HALT
11.4.5 Interrupts
Interrupt Event Output Compare 1 event Output Compare 2 event Timer Overflow event Event Flag OCF1 OCF2 TOF Enable Control Bit OCIE TOIE Exit from Wait Yes Yes Yes Exit from Halt No No No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask bits in the CC register are reset (RIM instruction).
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16-BIT TIMER (Cont'd) 11.4.6 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (TCR1) Read/Write Reset Value: 0000 0000 (00h)
7 0 OCIE TOIE FOLV2 FOLV1 OLVL2 0 0 OLVL1
Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. Bit 1 = Reserved, forced by hardware to 0. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register.
Bit 7 = Reserved, forced by hardware to 0. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
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16-BIT TIMER (Cont'd) CONTROL REGISTER 2 (TCR2) Read/Write Reset Value: 0000 0000 (00h)
7 OC1E OC2E 0 0 CC1 CC0 0 0 0
STATUS REGISTER (TSR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.
7 0 OCF1 TOF 0 OCF2 0 0 0 0
Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Bit 6 = OC2E Output Compare 2 Pin Enable. This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. Bits 5:4 = Reserved, forced by hardware to 0.
Bit 7 = Reserved, forced by hardware to 0. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = Reserved, forced by hardware to 0.
Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 27. Clock Control Bits
Timer Clock fCPU / 4 fCPU / 2 fCPU / 8 Reserved CC1 0 0 1 1 CC0 0 1 0 1
Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bits 2:0 = Reserved, forced by hardware to 0.
Bits 1:0 = Reserved, forced by hardware to 0.
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16-BIT TIMER (Cont'd) OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0
COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
LSB
OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 MSB 0 LSB
OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 MSB 0 LSB
ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
7 MSB 0 LSB
OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 MSB 0 LSB
ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 MSB 0 LSB
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16-BIT TIMER (Cont'd) Table 28. 16-Bit Timer Register Map and Reset Values
Address (Hex.) 20 21 22 23 24 25 26 27 28 29 2A Register Name TCR1 Reset Value TCR2 Reset Value TSR Reset Value CHR Reset Value CLR Reset Value ACHR Reset Value ACLR Reset Value OC1HR Reset Value OC1LR Reset Value OC2HR Reset Value OC2LR Reset Value 7 0 0 OC1E 0 0 0 MSB 1 MSB 1 MSB 1 MSB 1 MSB 1 MSB 0 MSB 1 MSB 0 6 OCIE 0 OC2E 0 OCF1 0 1 1 1 1 0 0 0 0 5 TOIE 0 0 0 TOF 0 1 1 1 1 0 0 0 0 4 FOLV2 0 0 0 0 0 1 1 1 1 0 0 0 0 3 FOLV1 0 CC1 0 OCF2 0 1 1 1 1 0 0 0 0 2 OLVL2 0 CC0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 OLVL1 0 0 0 0 0 LSB 1 LSB 0 LSB 1 LSB 0 LSB 0 LSB 0 LSB 0 LSB 0
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11.5 PWM/BRM GENERATOR (DAC) 11.5.1 Introduction This PWM/BRM peripheral includes a 6-bit Pulse Width Modulator (PWM) and a 4-bit Binary Rate Multiplier (BRM) Generator. It allows the digital to analog conversion (DAC) when used with external filtering. Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map. 11.5.2 Main Features s Fixed frequency: fCPU/64 s Resolution: TCPU 10 s Steps of VDD/2 (5mV if VDD=5V) 11.5.3 Functional Description The 10 bits of the 10-bit PWM/BRM are distributed as 6 PWM bits and 4 BRM bits. The generator consists of a 10-bit counter (common for all channels), a comparator and the PWM/BRM generation logic. PWM Generation The counter increments continuously, clocked at internal CPU clock. Whenever the 6 least significant bits of the counter (defined as the PWM counter) overflow, the output level for all active channels is set. The state of the PWM counter is continuously compared to the PWM binary weight for each channel, as defined in the relevant PWM register, and when a match occurs the output level for that channel is reset. This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. This provides an analog voltage proportional to the average charge passed to the external capacitor. Thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable. Each output may individually have its polarity inverted by software, and can also be used as a logical output.
Figure 52. PWM Generation
COUNTER 63 COMPARE VALUE OVERFLOW OVERFLOW OVERFLOW
000
t
PWM OUTPUT
t
TCPU x 64
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PWM/BRM GENERATOR (Cont'd) PWM/BRM Outputs The PWM/BRM outputs are assigned to dedicated pins. The PWM/BRM outputs can be connected to an RC filter (see Figure 53 for an example). The RC filter time must be higher than TCPUx64. Figure 53. Typical PWM Output Filter
Table 29. 6-Bit PWM Ripple After Filtering
Cext (F) 0.128 1.28 12.8 V RIPPLE (mV) 78 7.8 0.78
OUTPUT STAGE Rext
OUTPUT VOLTAGE Cext
With RC filter (R=1K), fCPU = 8 MHz VDD = 5V PWM Duty Cycle 50% R=R ext Note: after a reset these pins are tied low by default and are not in a high impedance state.
Figure 54. PWM Simplified Voltage Output After Filtering
V DD PWMOUT 0V V DD OUTPUT VOLTAGE Vripple (mV) VOUTAVG
0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"
V
DD
PWMOUT 0V V
DD
V ripple (mV) OUTPUT VOLTAGE 0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE"
V OUTAVG
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PWM/BRM GENERATOR (Cont'd) BRM Generation The BRM bits allow the addition of a pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of "fine-tuning" the PWM Duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. The incremental pulses (with duration of T CPU) are added to the beginning of the original PWM pulse. The PWM intervals which are added to are specified in the 4-bit BRM register and are encoded as shown in the following table. The BRM values shown may be combined together to provide a summation of the incremental pulse intervals specified. The pulse increment corresponds to the PWM resolution. For example,if - Data 18h is written to the PWM register - Data 06h (00000110b) is written to the BRM register - with a 8MHz internal clock (125ns resolution) Then 3.0 s-long pulse will be output at 8 s intervals, except for cycles numbered 2,4,6,10,12,14, where the pulse is broadened to 3.125 s. Figure 55. BRM pulse addition (PWM > 0)
Note. If 00h is written to both PWM and BRM registers, the generator output will remain at "0". Conversely, if both registers hold data 3Fh and 0Fh, respectively, the output will remain at "1" for all intervals 1 to 15, but it will return to zero at interval 0 for an amount of time corresponding to the PWM resolution (TCPU). An output can be set to a continuous "1" level by clearing the PWM and BRM values and setting POL = "1" (inverted polarity) in the PWM register. This allows a PWM/BRM channel to be used as an additional I/O pin if the DAC function is not required.
Table 30. Bit BRM Added Pulse Intervals (Interval #0 not selected).
BRM 4 - Bit Data 0000 0001 0010 0100 1000 Incremental Pulse Intervals none i=8 i = 4,12 i = 2,6,10,14 i = 1,3,5,7,9,11,13,15
m=0 TCPU x 64
m=1 TCPU x 64
m=2 TCPU x 64
m = 15 TCPU x 64
TCPU x 64 increment
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PWM/BRM GENERATOR (Cont'd) Figure 56. Simplified Filtered Voltage Output Schematic with BRM Added
= VDD PWMOUT 0V VDD BRM = 1
OUTPUT VOLTAGE
=
BRM = 0
0V
TCPU
BRM EXTENDED PULSE
Figure 57. Graphical Representation of 4-Bit BRM Added Pulse Positions
BRM VALUE 0 1 2 3 4
PWM Pulse Number (0-15) 5 6 7 8 9 10 11 12 13 14 15
0001 bit0=1 0010 bit1=1 0100 bit2=1 1000 bit3=1 Examples 0110 1111
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PWM/BRM GENERATOR (Cont'd) Figure 58. Precision for PWM/BRM Tuning for VOUTEFF (After filtering)
11.5.4 Register Description On a channel basis, the 10 bits are separated into two data registers: Note: The number of PWM and BRM channels available depends on the device. Refer to the device pin description and register map. PULSE BINARY WEIGHT REGISTERS (PWMi) Read / Write Reset Value 1000 0000 (80h)
7 1 POL P5 P4 P3 P2 P1 0 P0
BRM REGISTERS Read / Write Reset Value: 0000 0000 (00h)
7 B7 B6 B5 B4 B3 B2 B1 0 B0
These registers define the intervals where an incremental pulse is added to the beginning of the original PWM pulse. Two BRM channel values share the same register. Bit 7:4 = B[7:4] BRM Bits (channel i+1). Bit 3:0 = B[3:0] BRM Bits (channel i) Note: From the programmer's point of view, the PWM and BRM registers can be regarded as being combined to give one data value.
Bit 7 = Reserved (Forced by hardware to "1") Bit 6 = POL Polarity Bit for channel i. 0: The channel i outputs a "1" level during the binary pulse and a "0" level after. 1: The channel i outputs a "0" level during the binary pulse and a "1" level after. Bit 5:0 = P[5:0] PWM Pulse Binary Weight for channel i. This register contains the binary value of the pulse. For example :
1 POL P P P P P
P
+
B
B
B
B
Effective (with external RC filtering) DAC value
1 POL P P P P P P B B B B
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PULSE WIDTH MODULATION (Cont'd) Table 31. PWM Register Map and Reset Values
Address (Hex.) 4D 4E 4F Register Name PWM0 Reset Value BRM10 Reset Value PWM1 Reset Value 7 1 1 B7 0 1 1 6 POL 0 B6 0 POL 0 5 P5 0 B5 0 P5 0 4 P4 0 B4 0 P4 0 3 P3 0 B3 0 P3 0 2 P2 0 B2 0 P2 0 1 P1 0 B1 0 P1 0 0 P0 0 B0 0 P0 0
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11.6 SERIAL PERIPHERAL INTERFACE (SPI) 11.6.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system. 11.6.2 Main Features s Full duplex synchronous transfers (on 3 lines) s Simplex synchronous transfers (on 2 lines) s Master or slave operation s Six master mode frequencies (fCPU/2 max.) s fCPU/2 max. slave mode frequency s SS Management by software or hardware s Programmable clock polarity and phase s End of transfer interrupt flag s Write collision, Master Mode Fault and Overrun flags 11.6.3 General Description Figure 59 shows the serial peripheral interface (SPI) block diagram. There are 3 registers: - SPI Control Register (SPICR) - SPI Control/Status Register (SPICSR) - SPI Data Register (SPIDR) The SPI is connected to external devices through 3 pins: - MISO: Master In / Slave Out data - MOSI: Master Out / Slave In data - SCK: Serial Clock out by SPI masters and input by SPI slaves - SS: Slave select: This input signal acts as a `chip select' to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.
Figure 59. Serial Peripheral Interface Block Diagram
Data/Address Bus SPIDR Read Read Buffer Interrupt request
MOSI MISO
8-Bit Shift Register
7 SPIF WCOL OVR MODF 0
SPICSR
SOD SSM
0 SSI
SOD bit
Write
SS
SPI STATE CONTROL
7 SPIE
1 0
SCK
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
SS
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 60. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first). The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device reFigure 60. Single Master/ Single Slave Application
sponds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin). To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible). Four possible data/clock timing relationships may be chosen (see Figure 63) but master and slave must be programmed with the same timing mode.
MASTER MSBit LSBit MISO MISO MSBit
SLAVE LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI CLOCK GENERATOR
SCK SS +5V
SCK SS
Not used if SS is managed by software
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 62) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register. In Master mode: - SS internal must be held high continuously
In Slave Mode: There are two cases depending on the data/clock timing relationship (see Figure 61): If CPHA=1 (data latched on 2nd clock edge): - SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to VSS, or made free for standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the in the SPICSR register) If CPHA=0 (data latched on 1st clock edge): - SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the shift register (see Section 11.6.5.3).
Figure 61. Generic SS Timing Diagram
MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1)
Byte 1
Byte 2
Byte 3
Figure 62. Hardware/Software Slave Select Management SSM bit
SSI bit SS external pin
1 0
SS internal
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following two steps in order (if the SPICSR register is not written first, the SPICR register setting may be not taken into account): 1. Write to the SPICSR register: - Select the clock frequency by configuring the SPR[2:0] bits. - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 63 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. - Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 2. Write to the SPICR register: - Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). The transmit sequence begins when software writes a byte in the SPIDR register. 11.6.3.4 Master Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
11.6.3.5 Slave Mode Operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: - Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 63). Note: The slave must have the same CPOL and CPHA settings as the master. - Manage the SS pin as described in Section 11.6.3.2 and Figure 61. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions. 11.6.3.6 Slave Mode Transmit Sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin. When data transfer is complete: - The SPIF bit is set by hardware - An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.6.5.2).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 63). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data capture clock edge Figure 63. Data Clock Timing Diagram
Figure 63, shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.
CPHA =1
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
CPHA =0
SCK (CPOL = 1) SCK (CPOL = 0)
MISO (from master) MOSI (from slave) SS (to slave)
CAPTURE STROBE
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.5 Error Flags 11.6.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: - The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. - The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. - The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device, the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with the MODF bit set. The MODF bit indicates that there might have been a multi-master conflict and allows software to handle this using an interrupt routine and either perform to a reset or return to an application default state.
11.6.5.2 Overrun Condition (OVR) An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte. When an Overrun occurs: - The OVR bit is set and an interrupt request is generated if the SPIE bit is set. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost. The OVR bit is cleared by reading the SPICSR register. 11.6.5.3 Write Collision Error (WCOL) A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful. Write collisions can occur both in master and slave mode. See also Section 11.6.3.2 Slave Select Management. Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation. The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Figure 64).
Figure 64. Clearing the WCOL bit (Write Collision Flag) Software Sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step Read SPICSR
RESULT
2nd Step
Read SPIDR
SPIF =0 WCOL=0
Clearing sequence before SPIF = 1 (during a data byte transfer) 1st Step 2nd Step Read SPICSR
RESULT
Read SPIDR
WCOL=0
Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.5.4 Single Master System A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 65). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission. For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register. Other transmission security methods can use ports for handshake lines or data bytes with command fields.
Figure 65. Single Master / Multiple Slave Configuration
SS SCK Slave MCU MOSI MISO SCK Slave MCU
SS SCK Slave MCU
SS SCK Slave MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO SCK Master MCU 5V SS Ports
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.6 Low Power Modes
Mode WAIT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with "exit from HALT mode" capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device.
HALT
form an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see Section 11.6.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode. 11.6.7 Interrupts
Interrupt Event SPI End of Transfer Event Master Mode Fault Event Overrun Error Event Flag SPIF MODF OVR SPIE Enable Control Bit Exit from Wait Yes Yes Yes Exit from Halt Yes No No
11.6.6.1 Using the SPI to wakeup the MCU from Halt mode In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to per-
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL PERIPHERAL INTERFACE (Cont'd) 11.6.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh)
7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 0 SPR0
Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1, MODF=1 or OVR=1 in the SPICSR register Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.6.5.1 Master Mode Fault (MODF)). The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins. 0: I/O pins free for general purpose I/O 1: SPI I/O pin alternate functions enabled Bit 5 = SPR2 Divider Enable. This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 32 SPI Master mode SCK Frequency. 0: Divider by 2 enabled 1: Divider by 2 disabled Note: This bit has no effect in slave mode. Bit 4 = MSTR Master Mode. This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0 (see Section 11.6.5.1 Master Mode Fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: SCK pin has a low level idle state 1: SCK pin has a high level idle state Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Bit 2 = CPHA Clock Phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. Note: The slave must have the same CPOL and CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the SPI serial clock SCK output by the SPI in master mode. Note: These 2 bits have no effect in slave mode. Table 32. SPI Master mode SCK Frequency Serial Clock fCPU/2 fCPU/4 fCPU/8 fCPU/16 fCPU/32 fCPU/64 SPR2 1 0 0 1 0 0 SPR1 0 0 0 1 1 1 SPR0 0 0 1 0 0 1
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SERIAL PERIPHERAL INTERFACE (Cont'd) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h)
7 SPIF WCOL OVR MODF SOD SSM 0 SSI
Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.6.3.2 Slave Select Management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a `chip select' by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 64). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.6.5.2). An interrupt is generated if SPIE = 1 in SPICSR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.6.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICSR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared.
The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Figure 59).
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SERIAL PERIPHERAL INTERFACE (Cont'd) Table 33. SPI Register Map and Reset Values
Address (Hex.) 19 1A 1B Register Label SPIDR Reset Value SPICR Reset Value SPICSR Reset Value 7 MSB x SPIE 0 SPIF 0 6 5 4 3 2 1 0 LSB x SPR0 x SSI 0
x SPE 0 WCOL 0
x SPR2 0 OVR 0
x MSTR 0 MODF 0
x CPOL x 0
x CPHA x SOD 0
x SPR1 x SSM 0
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11.7 IC SINGLE MASTER BUS INTERFACE (I2C) 11.7.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides single master functions, and controls all I2C bus-specific sequencing, protocol and timing. It supports fast IC mode (400kHz). 11.7.2 Main Features - Parallel bus /I2C protocol converter - Interrupt generation - Standard I2C mode /Fast I2C mode - 7-bit Addressing 2 s I C single Master Mode - End of byte transmission flag - Transmitter/Receiver flag - Clock generation 11.7.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus Figure 66. I2C BUS Protocol SDA MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION
VR02119B
and a Fast I2C bus. This selection is made by software. Mode Selection The interface can operate in the two following modes: - Master transmitter/receiver By default, it is idle. The interface automatically switches from idle to master after it generates a START condition and from master to idle after it generates a STOP condition. Communication Flow The interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition is the address byte. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 66.
ACK
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IC SINGLE MASTER BUS INTERFACE (Cont'd) Acknowledge may be enabled and disabled by software. The speed of the I2C interface may be selected between Standard (0-100KHz) and Fast I2C (100400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. Figure 67. I2C Interface Block Diagram
The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistance used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
DATA REGISTER (DR)
SDAI SDA DATA CONTROL DATA SHIFT REGISTER
SCLI SCL CLOCK CONTROL
CLOCK CONTROL REGISTER (CCR)
CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) STATUS REGISTER 2 (SR2) CONTROL LOGIC
INTERRUPT
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IC SINGLE MASTER BUS INTERFACE (Cont'd) 11.7.4 Functional Description (Master Mode) Refer to the CR, SR1 and SR2 registers in Section 11.7.7. for the bit definitions. By default the I2C interface operates in idle mode (M/IDL bit is cleared) except when it initiates a transmit or receive sequence. To switch from default idle mode to Master mode a Start condition generation is needed. Start condition and Transmit Slave address Setting the START bit causes the interface to switch to Master mode (M/IDL bit set) and generates a Start condition. Once the Start condition is sent: - The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address byte, holding the SCL line low (see Figure 68 Transfer sequencing EV1). Then the slave address byte is sent to the SDA line via the internal shift register. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): - The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 68 Transfer sequencing EV2). Next the master must enter Receiver or Transmitter mode. Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:
- Acknowledge pulse if if the ACK bit is set - EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 68 Transfer sequencing EV3). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to idle mode (M/IDL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 68 Transfer sequencing EV4). When the acknowledge bit is received, the interface sets: - EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to idle mode (M/IDL bit cleared). Error Case - AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. Note: The SCL line is not held low.
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IC SINGLE MASTER BUS INTERFACE (Cont'd) Figure 68. Transfer Sequencing Master receiver:
S EV1 Address A EV2 Data1 A EV3 Data2 A EV3 ..... DataN NA EV3 P
Master transmitter:
S EV1 Address A EV2 EV4 Data1 A EV4 Data2 A EV4 ..... DataN A EV4 P
Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV1: EV2: EV3: EV4: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
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IC SINGLE MASTER BUS INTERFACE (Cont'd) 11.7.5 Low Power Modes
Mode
2
Description No effect on I C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with "exit from HALT mode" capability.
WAIT HALT
11.7.6 Interrupts Figure 69. Event Flags and Interrupt Generation
ITE BTF SB AF * INTERRUPT
EVF
can * EVF * also be set by EV2 or an error from the SR2 register.
Interrupt Event End of Byte Transfer Event Start Bit Generation Event (Master mode) Acknowledge Failure Event
Event Flag BTF SB AF
Enable Control Bit ITE
Exit from Wait Yes Yes Yes
Exit from Halt No No No
Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bits in the CC register are reset (RIM instruction).
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IC SINGLE MASTER BUS INTERFACE (Cont'd) 11.7.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h)
7 0 0 PE 0 START ACK STOP 0 ITE
- In master mode: 0: No start generation 1: Repeated start generation - In idle mode: 0: No start generation 1: Start generation when the bus is free Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after a data byte is received Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Stop condition is sent. - In Master mode only: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 4 for the relationship between the events and the interrupt. SCL is held low when the SB or BTF flags or an EV2 event (See Figure 68) is detected.
Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master capability Notes: - When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 - When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. - To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 = Reserved. Forced to 0 by hardware. Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1).
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IC SINGLE MASTER BUS INTERFACE (Cont'd) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h)
7 EVF 0 TRA 0 BTF 0 M/IDL 0 SB
Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 68. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: - BTF=1 (Byte received or transmitted) - SB=1 (Start condition generated) - AF=1 (No acknowledge received after byte transmission if ACK=1) - Address byte successfully transmitted. Bit 6 = Reserved. Forced to 0 by hardware. Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 = Reserved. Forced to 0 by hardware. Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading
SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). - Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV2 event (See Figure 68). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. - Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 = Reserved. Forced to 0 by hardware. Bit 1 = M/IDL Master/Idle. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after generating a Stop condition on the bus. It is also cleared when the interface is disabled (PE=0). 0: Idle mode 1: Master mode Bit 0 = SB Start bit generated. This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated
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IC SINGLE MASTER BUS INTERFACE (Cont'd) I2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h)
7 0 0 0 AF 0 0 0 0 0
Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 3:0 = Reserved. Forced to 0 by hardware.
Bit 7:5 = Reserved. Forced to 0 by hardware.
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IC SINGLE MASTER BUS INTERFACE (Cont'd) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h)
7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 CC0
I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h)
7 D7 D6 D5 D4 D3 D2 D1 0 D0
Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC6-CC0 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). - Standard mode (FM/SM=0): FSCL <= 100kHz FSCL = FCPU/(2x([CC6..CC0]+2)) - Fast mode (FM/SM=1): FSCL > 100kHz FSCL = FCPU/(3x([CC6..CC0]+2)) Note: The programmed FSCL assumes no load on SCL and SDA lines.
Bit 7:0 = D7-D0 8-bit Data Register. These bits contains the byte to be received or transmitted on the bus. - Transmitter mode: Byte transmission start automatically when the software writes in the DR register. - Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the next data bytes are received one by one after reading the DR register.
Table 34. I2C Register Map
Address (Hex.) 40 41 42 43 46 Register Name CR Reset Value SR1 Reset Value SR2 Reset Value CCR Reset Value DR Reset Value 0 EVF 0 0 FM/SM 0 DR7 0 0 0 0 CC6 0 DR6 0 7 6 5 PE 0 TRA 0 0 CC5 0 DR5 0 0 0 AF 0 CC4 0 DR4 0 4 3 START 0 BTF 0 0 CC3 0 DR3 0 2 ACK 0 0 0 CC2 0 DR2 0 1 STOP 0 M/IDL 0 0 CC1 0 DR1 0 0 ITE 0 SB 0 0 CC0 0 DR0 0
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11.8 8-BIT A/D CONVERTER (ADC) 11.8.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register. 11.8.2 Main Features s 8-bit conversion s Up to 16 channels with multiplexed input s Linear successive approximation s Data register (DR) which contains the results s Conversion complete status flag s On/off bit (to reduce consumption) The block diagram is shown in Figure 70. Figure 70. ADC Block Diagram 11.8.3 Functional Description 11.8.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. See electrical characteristics section for more details.
fCPU
DIV 4
fADC
COCO
0
ADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
HOLD CONTROL
AIN1
R ADC
ANALOG MUX
ANALOG TO DIGITAL CONVERTER
AINx
CADC
ADCDR
D7
D6
D5
D4
D3
D2
D1
D0
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8-BIT A/D CONVERTER (ADC) (Cont'd) 11.8.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.8.3.3 A/D Conversion Phases The A/D conversion is based on two conversion phases as shown in Figure 71: s Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. s A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximation cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 11.8.3.4 Software Procedure Refer to the control/status register (CSR) and data register (DR) in Section 11.8.6 for the bit definitions and to Figure 71 for the timings. ADC Configuration The total duration of the A/D conversion is 12 ADC clock periods (1/fADC=4/fCPU). The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the I/O ports chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the CSR register: - Select the CH[3:0] bits to assign the analog channel to be converted. ADC Conversion In the CSR register: - Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete - The COCO bit is set by hardware. - No interrupt is generated. - The result is in the DR register and remains valid until the next conversion has ended. A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion. Figure 71. ADC Conversion Timings
ADON tCONV
ADCCSR WRITE OPERATION
HOLD CONTROL
tLOAD
COCO BIT SET
11.8.4 Low Power Modes
Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 11.8.5 Interrupts None
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8-BIT A/D CONVERTER (ADC) (Cont'd) 11.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h)
7
COCO 0 ADON 0 CH3 CH2 CH1
DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h)
0
CH0
7
D7 D6 D5 D4 D3 D2 D1
0
D0
Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert.
Channel Pin* AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag.
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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8-BIT A/D CONVERTER (ADC) (Cont'd)
Table 35. ADC Register Map and Reset Values
Address (Hex.) 0012h 0013h Register Label ADCDR Reset Value ADCCSR Reset Value 7 D7 0 COCO 0 6 D6 0 0 5 D5 0 ADON 0 4 D4 0 0 3 D3 0 CH3 0 2 D2 0 CH2 0 1 D1 0 CH1 0 0 D0 0 CH0 0
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12 INSTRUCTION SET
12.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5
The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do Table 36. CPU Addressing Mode Overview
Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip Syntax
so, most of the addressing modes may be subdivided in two sub-modes called long and short: - Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. - Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.
Destination
Pointer Address (Hex.)
Pointer Size (Hex.)
Length (Bytes) +0 +1
00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word
+1 +2 +0 +1 +2 +2 +2 +2 +2 +1 +2 +1 +2 +2 +3
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INSTRUCTION SET OVERVIEW (Cont'd) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask (level 3) Reset Interrupt Mask (level 0) Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles
12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
12.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function
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INSTRUCTION SET OVERVIEW (Cont'd) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Table 37. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes
Long and Short Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function
12.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Available Relative Direct/Indirect Instructions JRxx CALLR Function Conditional Jump Call Relative
The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode.
Short Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear
Function
Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine
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INSTRUCTION SET OVERVIEW (Cont'd) 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP
be subdivided into 13 main groups as illustrated in the following table:
Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if Port B INT pin = 1 Jump if Port B INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I1:0 = 11 Jump if I1:0 <> 11 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) jrf * (no Port B Interrupts) (Port B interrupt) H=1? H=0? I1:0 = 11 ? I1:0 <> 11 ? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Pop CC, A, X, PC inc X jp [TBL.w] reg, M tst(Reg - M) A = FFH-A dec Y reg, M reg reg, M reg, M 1 I1 H 0 I0 N N Z Z C M 0 N N N 1 Z Z Z C 1 Function/Example A=A+M+C A=A+M A=A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M C C Dst Src M M M M I1 H H H I0 N N N N N Z Z Z Z Z C C C
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INSTRUCTION SET OVERVIEW (Cont'd)
Mnemo JRULE LD MUL NEG NOP OR POP PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Description Jump if (C + Z = 1) Load Multiply Negate (2's compl) No Operation OR operation Pop from the Stack Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR A = A XOR M A M I1:0 = 10 (level 0) C <= A <= C C => A => C S = Max allowed A=A-M-C C=1 I1:0 = 11 (level 3) C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A=A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt 1 1 1 0 N Z reg, M reg, M reg, M reg, M A reg, M M 1 1 N N 0 N N N N Z Z Z Z Z Z Z C C C C C A M N Z C 1 reg, M reg, M 1 0 N N Z Z C C A=A+M pop reg pop CC push Y C=0 A reg CC M M M M reg, CC 0 I1 H I0 N Z C N Z Function/Example Unsigned <= dst <= src X,A = X * A neg $10 reg, M A, X, Y reg, M M, reg X, Y, A 0 N Z N Z 0 C Dst Src I1 H I0 N Z C
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13 ELECTRICAL CHARACTERISTICS
13.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 13.1.1 Minimum and Maximum Values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 13.1.2 Typical Values Unless otherwise specified, typical data are based on TA=25C, VDD=5V (for the 4.5VVDD5.5V voltage range) and VDD=3.3V (for the 3VVDD4V voltage range). They are given only as design guidelines and are not tested. 13.1.3 Typical Curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 Loading Capacitor The loading conditions used for pin parameter measurement is shown in Figure 72. Figure 72. Pin Loading Conditions 13.1.5 Pin input Voltage The input voltage measurement on a pin of the device is described in Figure 73. Figure 73. Pin input Voltage
ST7 PIN
VIN
ST7 PIN
CL
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13.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi13.2.1 Voltage Characteristics
Symbol VDD - VSS VIN
1) & 2)
tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Ratings Supply voltage Input voltage on any pin Electro-static discharge voltage (Human Body Model)
Maximum value 6.0 VSS-0.3 to VDD+0.3 1500
Unit V
VESD(HBM)
13.2.2 Current Characteristics
Symbol IVDD IVSS IIO Ratings Total current into VDD power lines (source) 3) Total current out of VSS ground lines (sink) 3) Output current sunk by any standard I/O and control pin Output current sunk by any high sink I/O pin Output current source by any I/Os and control pin Injected current on VPP pin IINJ(PIN) 2) & 4) Injected current on RESET pin Injected current on OSC1 and OSC2 pins Injected current on any other pin IINJ(PIN)
2) 5) & 6) 5)
Maximum value 100 80 25 50 - 25 5 5 5 5 20
Unit
mA
Total injected current (sum of all I/O and control pins)
13.2.3 Thermal Characteristics
Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature Value -65 to +150 TBD Unit C C
Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for RESET, 10k for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN129/166
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13.3 OPERATING CONDITIONS 13.3.1 General Operating Conditions
Symbol Parameter Conditions Min 4.0 2.7 3.0 12 0 Max 5.5 5.5 5.5 12 70 Unit V V V MHz C
Supply voltage with USB peripheral enasee Figure 74 bled VDD Supply voltage with USB peripheral disasee Figure 74 bled and LVD off (ROM version) Supply voltage with USB peripheral disasee Figure 74 bled and LVD off (FLASH version) fOSC TA External clock frequency Ambient temperature range
Figure 74. fOSC Maximum Operating Frequency Versus VDD Supply Voltage 1)
fCPU [MHz]
FUNCTIONALITY GUARANTEED IN THIS AREA2)
8 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 4 3 2 0 2.0 See note 4 2.5 2.7 3.0 3.5 4.0 4.55 5.0 5.5 FUNCTIONALITY GUARANTEED IN THIS AREA EXCEPT USB CELL 3)
SUPPLY VOLTAGE [V]
Notes: A/D operation not guaranteed below 1MHz. 1. Operating conditions with TA=0 to +70C. 2. This mode is supported by all devices. 3. This mode is only supported by ST72(F)651AR6T1E ROM and Flash devices (without LVD) 4. The 2.7V-3.0V voltage range is only supported by ST72651AR6T1E ROM devices (without LVD)
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OPERATING CONDITIONS (Cont'd) 13.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fOSC, and TA.
Symbol VIT+ VITVhys fCUTOFF VtPOR Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) LVD voltage threshold hysteresis LVD filter cut-off frequency 2) VDD rise time 3) VIT+-VITNot detected by the LVD 0.3 Conditions Min 2.9 2.6 150 Typ 1) 3.5 3.1 300 10 10 Max 3.8 V 3.5 mV MHz. ms Unit
Notes: 1. LVD typical data are based on TA=25C. They are given only as design guidelines and are not tested. 2. Not tested, guaranteed by construction. 3. The VDD rise time condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
13.3.3 Power Supply Manager Characteristics Subject to general operating conditions for VDD, fOSC, and TA. Not guaranteed on LVD devices (without E suffix).
Symbol USBVIT+ USBVITUSBVhys VPLLmin48 VPLLmin40 Parameter Reset release threshold (VDD rise) Reset generation threshold (VDD fall) USB voltage threshold hysteresis Minimum voltage required for stable 48MHz PLL operation (PLL locked) Minimum voltage required for 40MHz PLL operation (PLL unlocked) Minimum voltage required for 24MHz PLL operation (PLL unlocked) Conditions Min 3.50 3.30 USBVIT+-USBVIT100 3.7
1)
Typ 3.80 3.65 200
Max 4.00
Unit
V 3.80 300 mV V V
3.4 1)
VPLLmin24
3.0 1)
V
1. Not tested, guaranteed by construction.
13.3.4 Storage Device Supply Characteristics Subject to general operating conditions for VDD, fOSC, and TA.
Symbol Parameter Voltage output for external storage device (Iload max = 50mA) Conditions USB Mode: VSET[1:0]=11 VDDF 10 01 00 Min 2.5 2.9 3.0 3.1 Typ 2.8 3.3 3.4 3.5 Max 3.2 3.6 3.8 3.9 V Unit
Note: In Stand-alone mode VDDF must be connected to VDD
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13.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be 13.4.1 RUN Mode
Symbol Parameter 2.7VVDD4.0V 4.0VVDD5.5V
added (except for HALT mode for which the clock is stopped).
Conditions
Typ 1)
Max 2)
Unit
Supply current in RUN mode 3) (see Figure 75) IDD Supply current in RUN mode 3) (see Figure 75)
fCPU=8MHz
14
20
mA
fCPU=3MHz
4
8
Figure 75. Typical IDD in RUN vs. fCPU
20 18 16 14 Idd (mA) 12 10 8 6 8 MHz 4 2 0 2 3 4 Vdd (V) 5 6 7 6 MHz 3 MHz
Notes: 1. Typical data are based on TA=25C, VDD=5V (4.0VVDD5.5V range) and VDD=3.3V (2.7VVDD4.0V range). 2. Data based on characterization results, tested in production at VDD =5.5V. and fCPU = 8MHz 3. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.2 WAIT Mode
Symbol Parameter 2.7VVDD4.0V 4.0VVDD5.5V Conditions Typ 1) Max 2) Unit
Supply current in WAIT mode 3) (see Figure 76) IWFI Supply current in WAIT mode 3) (see Figure 76)
fCPU=8MHz
8
11
mA
fCPU=3MHz
3
6
Figure 76. Typical IDD in WAIT vs. fCPU
12
10 8
Idd wfi (mA)
6 4 8 MHz 2 6 MHz 3 MHz 0 2 3 4 Vdd (V) 5 6 7
Notes: 1. Typical data are based on TA=25C, VDD=5V (4VVDD5.5V range) and VDD=3.3V (2.7VVDD4.0V range). 2. Data based on characterization results, tested in production at VDD = 5.5V and fCPU = 8MHz. 3. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, LVD disabled.
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SUPPLY CURRENT CHARACTERISTICS (Cont'd) 13.4.3 HALT Mode
Symbol Parameter LVD OFF IHALT Supply current in HALT mode 2) LVD ON Conditions VDD=5.5V VDD=3.0V VDD=5.5V VDD=3.0V Typ 1) 3 1 110 60 Max TBD TBD TBD TBD A Unit
Notes:
1. Typical data are based on TA=25C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load).
13.4.4 SUSPEND Mode
Symbol ISUSP Parameter Supply current in SUSPEND mode
2)
Conditions LVD OFF LVD ON VDD=4-5.25V VDD=4-5.25V
Typ 1) 150 230
Max 3) 230 300
Unit A
Notes:
1. Typical data are based on TA=25C. 2. External pull-up (1.5k connected to USBVCC) and pull-down (15k connected to USBVSS) current not included. 3. TA=25C
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13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings
Symbol tc(INST) tv(IT) Parameter Instruction cycle time Interrupt reaction time tv(IT) = tc(INST) + 10
2)
Conditions fCPU=8MHz fCPU=8MHz
Min 2 250 10 1.25
Typ 1) 4 500
Max 12 1500 22 2.75
Unit tCPU ns tCPU s
13.5.2 External Clock Source
Symbol VOSC1H VOSC1L tw(OSC1H) tw(OSC1L) tr(OSC1) tf(OSC1) IL Parameter OSC1 input pin high level voltage OSC1 input pin low level voltage OSC1 high or low time 3) OSC1 rise or fall time 3) OSCx Input leakage current VSSVINVDD Conditions Min 0.7xVDD VSS 15 ns 15 1 A Typ Max VDD 0.3xVDD Unit V
Figure 77. Typical Application with an External Clock Source
90% VOSC1H 10% VOSC1L tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
OSC2
Not connected internally fOSC
EXTERNAL CLOCK SOURCE
OSC1
IL ST72XXX
Notes: 1. Data based on typical application software. Not tested in production. 2. Time measured between interrupt event and interrupt vector fetch. tc(INST) is the number of tCPU cycles needed to finish the current instruction execution. 3. Data based on design simulation and/or technology characteristics, not tested in production.
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13.6 MEMORY CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 13.6.1 RAM and Hardware Registers
Symbol VRM Parameter Data retention mode
1)
Conditions HALT mode (or RESET)
Min 2
Typ
Max
Unit V
13.6.2 FLASH Memory Operating Conditions: fCPU = 8 MHz.
DUAL VOLTAGE FLASH MEMORY Symbol Parameter fCPU VPP IPP tPROG tERASE tVPP tRET NRW Operating Frequency Programming Voltage VPP Current Byte Programming Time Sector Erasing Time Device Erasing Time Internal VPP Stabilization Time Data Retention Write Erase Cycles Conditions Read mode Write / Erase mode, TA=25C 4.0V <= VDD <= 5.5V Write / Erase TA=25C Min Typ Max 8 8 11.4 100 2 5 10 20 100 12.6 30 1) 500 1) 10 1) 10 1) Unit MHz V mA s sec s years cycles
TA 55C TA=25C
Note 1: Guaranteed by Design.
Figure 78. Two typical Applications with VPP Pin1)
VPP
PROGRAMMING TOOL
VPP 10k
ST72XXX
ST72XXX
Note 1: When the ICP mode is not required by the application, VPP pin must be tied to VSS.
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13.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 13.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. s FTB: Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed.
s
Symbol VFESD VFFTB
Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance
Conditions VDD=5V, TA=+25C, fOSC=8MHz conforms to IEC 1000-4-2
Neg 1) -1 -2
Pos 1) >1.5
Unit
Fast transient voltage burst limits to be apVDD=5V, TA=+25C, fOSC=8MHz plied through 100pF on VDD and VDDA pins conforms to IEC 1000-4-4 to induce a functional disturbance
kV 2
Figure 79. EMC Recommended star network power supply connection 2)
ST72XXX 10F 0.1F
ST7 DIGITAL NOISE FILTERING
VDD
VSS
VDD
POWER SUPPLY SOURCE
VSSA
EXTERNAL NOISE FILTERING
VDDA 0.1F
Notes: 1. Data based on characterization results, not tested in production. 2. The suggested 10F and 0.1F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
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EMC CHARACTERISTICS (Cont'd) 13.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] 3MHz 21 16 8 2 6MHz 28 30 31 4 dBV Unit
SEMI
Peak level
0.1MHz to 30MHz VDD=5V, TA=+25C, 30MHz to 130MHz TQFP64 package conforming to SAE J 1752/3 130MHz to 1GHz SAE EMI Level
Note 1. Data based on characterization results, not tested in production.
13.7.3 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note. 13.7.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins of the device (3 parts*(n+1) supply pin). One model is simulated: Human Body Model. This test conforms to the JESD22-A114A Absolute Maximum Ratings
Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model)
standard. See Figure 80 and the following test sequence. Human Body Model Test Sequence - CL is loaded through S1 by the HV pulse generator. - S1 switches position from generator to R. - A discharge from CL through R (body resistance) to the ST7 occurs. - S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.
Conditions TA=+25C
Maximum value 1) Unit 1500 V
Figure 80. Typical equivalent ESD Circuit
S1 R=1500
HIGH VOLTAGE PULSE GENERATOR
CL=100pF
ST7
S2
HUMAN BODY MODEL
Note 1: Data based on characterization results, not tested in production.
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EMC CHARACTERISTICS (Cont'd) 13.7.3.2 Static and Dynamic Latch-Up s LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/ JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note. s DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 81. For more details, refer to the AN1181 ST7 application note. 13.7.3.3 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It Electrical Sensitivities
Symbol LU DLU Parameter Static latch-up class Dynamic latch-up class
should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions TA=+25C TA=+85C TA=+125C VDD=5.5V, fOSC=4MHz, TA=+25C
Class 1) A A A A
Figure 81. Simplified Diagram of the ESD Generator for DLU
RCH=50M RD=330 DISCHARGE TIP VDD VSS HV RELAY
CS=150pF ESD GENERATOR 2)
ST7
DISCHARGE RETURN CONNECTION
Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger.
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EMC CHARACTERISTICS (Cont'd) 13.7.4 ESD Pin Protection Strategy To protect an integrated circuit against ElectroStatic Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure. An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 82 and Figure 83 for standard pins and in Figure 84 and Figure 85 for true open drain pins.
Standard Pin Protection To protect the output structure the following elements are added: - A diode to VDD (3a) and a diode from VSS (3b) - A protection device between VDD and VSS (4) To protect the input structure the following elements are added: - A resistor in series with the pad (1) - A diode to VDD (2a) and a diode from VSS (2b) - A protection device between VDD and VSS (4)
Figure 82. Positive Stress on a Standard Pad vs. VSS
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path Path to avoid
(3b) (2b)
VSS
VSS
Figure 83. Negative Stress on a Standard Pad vs. VDD
VDD VDD
(3a)
(2a)
(1) OUT (4) IN
Main path
(3b) (2b)
VSS
VSS
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EMC CHARACTERISTICS (Cont'd) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to VDD are not implemented. An additional local protection between the pad and VSS (5a & 5b) is implemented to completely absorb the positive ESD discharge. Multisupply Configuration When several types of ground (VSS, VSSA, ...) and power supply (VDD, VDDA, ...) are available for any reason (better noise immunity...), the structure shown in Figure 86 is implemented to protect the device against ESD.
Figure 84. Positive Stress on a True Open Drain Pad vs. VSS
VDD VDD
Main path Path to avoid
(1) OUT (4) IN
(5a)
(3b)
(2b)
(5b)
VSS
VSS
Figure 85. Negative Stress on a True Open Drain Pad vs. VDD
VDD VDD
Main path
(1) OUT (4) IN
(3b)
(3b)
(2b)
(3b)
VSS
VSS
Figure 86. Multisupply Configuration
VDD VDDA
VDDA
VSS
BACK TO BACK DIODE BETWEEN GROUNDS
VSSA
VSSA
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13.8 I/O PORT PIN CHARACTERISTICS 13.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys IL IS RPU CIO tf(IO)out tr(IO)out tw(IT)in Parameter Input low level voltage Input high level voltage Schmitt trigger voltage hysteresis 3) Input leakage current Static current consumption 4) Weak pull-up equivalent resistor 5) I/O pin capacitance 6) Output high to low level fall time 6) External interrupt pulse time 7) CL=50pF 6) Between 10% and 90% Output low to high level rise time 1 VSSVINVDD Floating input mode VIN=VSS VDD=5V VDD=3V 70 130 100 200 5 25 25 Conditions VDD = 5.0V VDD = 5.0V Min Vss 0.7xVDD 400 1 200 130 260 Typ 1) Max 0.3xVDD VDD Unit V mV A k pF ns tCPU
.Notes:
1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure ). Data based on design simulation and/or technology characteristics, not tested in production. 5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 89). This data is based on characterization results, tested in production at VDD=5V. 6. Data based on characterization results, not tested in production. 7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
Figure 87Two typical Applications with unused I/O Pin
VDD 10k
ST72XXX
10k UNUSED I/O PORT UNUSED I/O PORT
ST72XXX
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. I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 88. VIL and VIH vs. VDD with VIN=VSS
3.5
3 2.5 Vil and Vih(V) 2
1.5 1 Vih 0.5 0 2.5 Vil
3
3.5
4
4.5
5
5.5
6
Vdd (V)
Figure 89. Typical IPU vs. VDD with VIN=VSS
0 -10 -20
Figure 90. Typical R PU vs. VDD with VIN=VSS
300 250 Rpu (Kohms) 200 150 100 50 0 2
2 3 4 Vdd (V) 5 6 7
-30 Ipu (A) -40 -50 -60 -70 -80 -90
3
4 Vdd (V)
5
6
7
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I/O PORT PIN CHARACTERISTICS (Cont'd) 13.8.2 Output Driving Current Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 91 and Figure 94) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 93 and Figure 95) Output high level voltage for an I/O pin when 8 pins are sourced at same time (see Figure 92 and Figure 96) VDD=5V Conditions IIO=+5mA IIO=+2mA IIO=+20mA IIO=+8mA IIO=-5mA IIO=-2mA VDD-1.4 VDD-0.7 Min Max 1.2 0.5 1.3 0.6 V Unit
VOL 1)
VOH 2)
Figure 91. Typical VOL at VDD=5V (standard)
Figure 93. Typical VOL at VDD=5V (high-sink)
0.7 0.6 0.5 Vol (V) 0.4 0.3 0.2 0.1 0 0 1 2 3 Iol (mA) 4 5 6 7
0.8 0.7 0.6 0.5 Vol (V) 0.4 0.3 0.2 0.1 0 0 5 10 15 Iol (mA) 20 25 30
Figure 92Typical VDD-VOH at VDD=5V
1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 -Ioh (mA) 4 5 6 7
Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
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I/O PORT PIN CHARACTERISTICS (Cont'd) Figure 94.Typical VOL vs. VDD (standard I/Os)
0.35
1
0.3 0.25 Vol (V) at lio=2mA 0.2 0.15 0.1 0.05 0 2 3 4 Vdd (V) 5 6 7
Vol (V) at lio=5mA
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 Vdd (V) 5 6 7
Figure 95. Typical VOL vs. VDD (high-sink I/Os)
0.5 0.45 0.4
1.4 1.2 Vol (V) at lio=20mA 1 0.8 0.6 0.4 0.2 1.6
Vol (V) at lio=8mA
0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
2
3
4 Vdd (V)
5
6
7
0 2 3 4 Vdd (V) 5 6 7
Figure 96. Typical VOH vs. VDD
0.7 0.6 Vdd-Voh (V) at lio=2mA
3
2.5
0.5
Vdd-Voh (V) at lio=5mA
0.4 0.3 0.2 0.1
2
1.5
1
0.5
0 2 3 4 Vdd (V)
Vdd (V)
5
6
7
0 2 3 4 5 6 7
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13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH Vhys VOL RON Parameter Input low level voltage
2)
Conditions VDD=5V VDD=5V IIO=+5mA IIO=+2mA VDD=5V VDD=3.3V
Min VSS 0.7xVDD
Typ 1)
Max 0.3xVDD VDD
Unit V mV
Input high level voltage 2) Schmitt trigger voltage hysteresis 3) Output low level voltage 4) Weak pull-up equivalent resistor 5)
400 VDD=5V VIN=VSS 0.68 0.28 70 130 100 200 4 20 100 0.95 0.45 130 260
V k 1/fSFOSC s ns
tw(RSTL)out Generated reset pulse duration th(RSTL)in tg(RSTL)in
8) Figure
External pin or internal reset sources
External reset pulse hold time 6) Filtered glitch duration 7)
97. Typical Application with RESET pin
VDD ST72XXX
AL
PT
IO
VDD
VDD RON 0.1F 4.7k RESET 0.1F
N
INTERNAL RESET CONTROL
O
EXTERNAL RESET CIRCUIT 8)
WATCHDOG RESET LVD RESET
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD=5V. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Not tested in production. 5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics described in Figure 97). This data is based on characterization results, not tested in production. 6. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored. 7. The reset network protects the device against parasitic resets, especially in a noisy environment. 8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
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CONTROL PIN CHARACTERISTICS (Cont'd) 13.9.2 VPP Pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol VIL VIH IL Parameter Input low level voltage Input leakage current
1)
Conditions
Min VSS VDD-0.1
Max 0.2 12.6 1
Unit
V
Input high level voltage 1) VIN=VSS
A
Figure 98. Two typical Applications with VPP Pin 2)
VPP
PROGRAMMING TOOL
VPP
ST72XXX
10k
ST72XXX
Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2. When the ICP mode is not required by the application, VPP pin must be tied to VSS.
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13.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. 13.10.1 Watchdog Timer
Symbol tw(WDG) Parameter Watchdog time-out duration Conditions Min 65,536 fCPU=8MHz 8.192 Typ Max 4,194,304 524.288 Unit tCPU ms
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).
13.10.2 PWM Generator
Symbol T Res s Parameter Repetition rate Resolution Output step Conditions TCPU =125ns TCPU =125ns VDD=5V Min Typ 125 125 5 Max Unit KHz ns mV
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13.11 COMMUNICATION INTERFACE CHARACTERISTICS 13.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for V DD, fOSC, and TA unless otherwise specified.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(SS) th(SS) tw(SCKH) tw(SCKL) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) tv(SO) th(SO) tv(MO) th(MO) Parameter Master SPI clock frequency fCPU=8MHz Slave fCPU=8MHz SPI clock rise and fall time SS setup time SS hold time SCK high and low time Data input setup time Data input hold time Data output access time Data output disable time Data output valid time Data output hold time Data output valid time Data output hold time Slave Slave Master Slave Master Slave Master Slave Slave Slave Slave (after enable edge) Master (before capture edge) 0 0.25 0.25 tCPU
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).
Conditions Min fCPU/128 0.0625 0 Max fCPU/4 2 fCPU/2 4 Unit
MHz
see I/O port pin description 120 120 100 90 100 100 100 100 0 120 240 120
ns
Figure 99. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT tsu(SS) SCK INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) MISO OUTPUT tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
tc(SCK)
th(SS)
tdis(SO)
see note 2
see note 2
MSB OUT
BIT6 OUT
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes: 1. Data based on design simulation and/or characterisation results, not tested in production. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. 3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) Figure 100. SPI Slave Timing Diagram with CPHA=11)
SS INPUT tsu(SS)
INPUT
tc(SCK)
th(SS)
CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK)
LSB OUT
SCK
tdis(SO)
MISO OUTPUT
see note 2
HZ
MSB OUT
BIT6 OUT
see note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Figure 101. SPI Master Timing Diagram
SS INPUT
1)
tc(SCK) CPHA=0 CPOL=0 SCK INPUT CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tv(MO) th(MI) tr(SCK) tf(SCK)
MSB IN
BIT6 IN
LSB IN
th(MO)
MOSI OUTPUT see note 2
MSB OUT
BIT6 OUT
LSB OUT
see note 2
Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 13.11.2 I2C - Inter IC Control Interface Refer to I/O port characteristics for more details on the input/output alternate function characteristics Subject to general operating conditions for VDD, (SDAI and SCLI). The ST7 I2C interface meets the fOSC, and TA unless otherwise specified. requirements of the Standard I2C communication protocol described in the following table.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) Cb SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 Parameter Standard mode I2C Min 1) 4.7 4.0 250 0
3)
Fast mode I2C Min 1) 1.3 0.6 100 0 2) 900 3) 300 300 Max 1)
Max 1)
Unit s
1000 300
20+0.1Cb 20+0.1Cb 0.6 0.6 0.6 1.3
ns
s ns ms 400 pF
tw(STO:STA) STOP to START condition time (bus free)
Figure 102. Typical Application with I2C Bus and Timing Diagram 4)
VDD 4.7k I2C BUS 4.7k VDD 100 100 SDAI SCLI
ST72XXX
REPEATED START START
tsu(STA)
SDA
tw(STO:STA)
START
tf(SDA)
SCK
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Notes: 1. Data based on standard I2C protocol requirement, not tested in production. 2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 13.11.3 I2C - Inter IC Control Interface
I2C-Bus Timings Parameter Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line 4.0 400 Standard I2C Min 4.7 4.0 4.7 4.0 4.7 0 (1) 250 1000 300 Max 1.3 0.6 1.3 0.6 0.6 0 (1) 100 20+0.1Cb 20+0.1Cb 0.6 400 300 300 0.9(2) Fast I2C Min Max Symbol TBUF THD:STA TLOW THIGH TSU:STA THD:DAT TSU:DAT TR TF TSU:STO Cb Unit ms s s s s ns ns ns ns ns pF
1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 2) The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal Cb = total capacitance of one bus line in pF
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd) 13.11.4 USB - Universal Bus Interface
USB DC Electrical Characteristics Parameter Input Levels: Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High USBVCC: voltage level 3) VOL VOH USBV RL of 1.5K ohms to 3.6V 1) RL of 15K ohm to VSS 1) VDD=4.0V - 5.5V ILOAD Max = 3mA 2.8 3.00 0.3 3.6 3.60 V V V VDI VCM VSE I(D+, D-) Includes VDI range 0.2 0.8 1.3 2.5 2.0 V V V Symbol Conditions Min. 2) Max. 2) Unit
Note 1: RL is the load connected on the USB drivers. Note 2: All the voltages are measured from the local ground potential. Note 3: An external decoupling capacitor (typical 100nF, min 47nF) must be connected between this pin and USBVSS. Figure 103. USB: Data Signal Rise and Fall Time
Differential Data Lines
VCRS
Crossover points
VSS tf tr
USB: Full speed electrical characteristics Parameter Driver characteristics: Rise time Fall Time Rise/ Fall Time matching Output signal Crossover Voltage tr tf trfm VCRS Note 1,CL=50 pF Note 1, CL=50 pF tr/tf 4 4 90 1.3 20 20 110 2.0 ns ns % V Symbol Conditions Min Max Unit
Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to Chapter 7 (Electrical) of the USB specification (version 1.1).
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13.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Symbol fADC VAIN RAIN CADC tSTAB tADC Parameter ADC clock frequency Conversion range voltage 2) VSSA 6 0 4) fCPU=8MHz, fADC=2MHz 6 4 8 External input resistor Internal sample and hold capacitor Stabilization time after ADC enable Conversion time (Sample+Hold) - Sample capacitor loading time - Hold conversion time Conditions Min Typ 1) Max 4 VDDA 10 3) Unit MHz V k pF s 1/fADC
Figure 104. Typical Application with ADC
VDD VT 0.6V RAIN VAIN CIO ~2pF VDD VDDA VT 0.6V IL 1A AINx
ADC
0.1F VSSA
ST72XXX
Notes: 1. Unless otherwise specified, typical data are based on TA=25C and VDD-VSS=5V. They are given only as design guidelines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS . 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid.
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8-BIT ADC CHARACTERISTICS (Cont'd) ADC Accuracy
Symbol ET E0 EG |ED| |EL| Parameter Total Unadjusted Error 1) Offset Error Gain Error 1) Differential linearity error Integral linearity error
1) 1)
Figure 105. ADC Accuracy Characteristics
Digital Result ADCDR 255 1LSB IDE AL 254 253 V V DDA SSA = ---------------------------------------256 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
(2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
5
6
7
253 254 255 256 VDDA
Notes: 1. ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6A and the effect on the ADC accuracy is a loss of 1 LSB for each 10K increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 2. Data based on characterization results with TA=25C. 3. Data based on characterization results over the whole temperature range, monitored in production.
Conditions
VDD=5.5V, 2) fCPU=1MHz Min -0.5 -2.0 Max 2.5 1.5 0 1.5 2.5
VDD=5.0V, 3) fCPU=8MHz 1) Min -1.0 -2.0 Max 2.5 1.5 0 1.5 2.5
VDD=3.3V, 3) fCPU=8MHz 1) Min -1.0 -2.0 Max 2.5 1.5 0 1.5 3.0
-
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin (LSBIDEAL)
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14 PACKAGE CHARACTERISTICS
14.1 PACKAGE MECHANICAL DATA Figure 106. 48-Pin Thin Quad Flat Package
mm Min 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 48 7 0 1.40 0.22 Typ Max 1.60 0.15 0.002 Min inches Typ Max 0.063 0.006
Dim.
D D1 A1 b A A2
A A1 A2 b C D D1 E E1 e L
h
1.45 0.053 0.055 0.057 0.27 0.007 0.009 0.011 0.20 0.004 0.354 0.276 0.354 0.276 0.020 3.5 0.039 7 0.75 0.018 0.024 0.030 0.008
E1
E
e
L1 L
c
L1 N
Number of Pins
Figure 107. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width
Dim.
h x 45x L A1 A a B D e C
mm Min 2.464 0.127 0.356 0.231 17.72 9 7.417 1.016 10.16 0 0.635 0 0.610 10.41 0.400 4 0.737 0.025 8 0 1.016 0.024 Typ Max Min 2.642 0.097 0.292 0.005 0.483 0.014 0.318 0.009 18.05 0.698 9 7.595 0.292
inches Typ Max 0.104 0.012 0.019 0.013 0.711 0.299 0.040 0.410 0.029 8 0.040
A A1 B C D E e
E
H
H h L N
Number of Pins 34
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PACKAGE MECHANICAL DATA (Cont'd) Figure 108. 64-Pin 10 x 10 Thin Quad Flat Package
0.10mm .004 seating plane
Dim A A1 A2 b C D D1 E E1 e K L L1
mm Min 0.05 Typ Max Min 1.60 0.15 0.002
inches Typ Max 0.063 0.006
1.35 1.40 1.45 0.053 0.055 0.057 0.17 0.22 0.27 0.007 0.009 0.011 0.09 12.00 10.00 12.00 10.00 0.50 0 3.5 1.00 64 ND 16 7 0 0.20 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.039 NE 16 7 0.008
0.45 0.60 0.75 0.018 0.024 0.030 Number of Pins
L1
L
N
K
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PACKAGE MECHANICAL DATA (Cont'd) Figure 109. Recommended Reflow Oven Profile (MID JEDEC) 250 200 Temp. [C] 150 100 50 0 100 200 300 400
ramp up 2C/sec for 50sec 150 sec above 183C 90 sec at 125C Tmax=220+/-5C for 25 sec
ramp down natural 2C/sec max
Time [sec]
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15 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM). FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured. 15.1 OPTION BYTE The option byte allows the hardware configuration of the microcontroller to be selected. The option byte has no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. This means that all the options have "1" as their default value. In masked ROM devices, the option byte is fixed in hardware by the ROM code (see option list)
7 PE5 PU PS PS MOD MOD 1 0 0 WDG USB FMP_ SW EN R Configuration Input floating Output Open Drain with Pull-up Input with pull-up Output push pull Input floating Output Open Drain Input floating Output push pull PE5PU OPTION PEOR.5 0 0 0 1 1 0 0 1 1 PEDDR.5 0 1 0 1 0 1 0 1
1
OPT5:4 = PSMOD[1:0] Power Supply Mode These option bits configure the power supply mode.
Mode Stand-alone mode forced Dual Supply (normal) Mode USB mode forced OPT5 0 x 1 OPT4 0 1 0
OPT3 = Reserved. Must be kept at 1. OPT2= WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT1 = USBEN 0: USBEN alternate function disabled. Port F4 is free for general purpose I/O 1: USBEN alternate function enabled on Port F4 (function controlled by hardware) OPT0= FMP_R Flash memory read-out protection This option indicates if the user flash memory is protected against read-out piracy. This protection is based on read and a write protection of the memory in test modes and IAP. Erasing the option bytes when the FMP_R option is selected will cause the whole user memory to be erased first, and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.4 on page 22 for more details. 0: Read-out protection enabled 1: Read-out protection disabled
OPT7 = Reserved. Must be kept at 1. OPT6 = PE5PU I/O Port PE5 Pull-up Option This option bit determines if a pull-up is connected on Port E5. 0: Pull up present on PE5 1: No pull-up on PE5 When PE5PU=00: - For input, software can enable or disable the pull-up by programming PEOR.5 and PEDDR.5=0. - For output, the pull-up is enabled when Open Drain is selected by programming PEOR.5= and PEDDR.5=1. Refer to the following table.
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15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM contents. The ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19 format generated by the development tool. All unused bytes must be set to FFh. Figure 110. Sales Type Coding Rules 2) Family (ROM, FLASH, FASTROM) Product Line (1,2,3 ...) Number of pins ROM size Package Temperature Range No LVD option ROM Code (three letters)
ST 7265 1 AR 6 T 1 E / xxx 0= 25C T=Thin Quad Flat Pack 6=32K AR = 64 pins (TQFP64 (10X10)) 4=16K C=48 pins L=34 pins
The customer code should be communicated to STMicroelectronics with the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
E= without LVD (external reset needed) No letter = with LVD
1= Standard (0 to +70C) M=Small Outline Package
Table 38. Ordering Information
Sales Type 1) 2) ST72F651AR6T1 ST72651AR6T1/xxx ST72652AR4T1/xxx ST72652C4T1/xxx ST72652L4M1/xxx ST72F651AR6T1E ST72651AR6T1E/xxx Program Memory (bytes) 32K 32K 16K 16K 16K 32K 32K FLASH ROM ROM ROM ROM FLASH ROM User RAM (bytes) 5K 5K 512 512 512 5K 5K Package Operating Voltage
TQFP 64 (10X10) 4.0V-5.5V TQFP48 SO34 TQFP 64 (10X10) 3.0V-5.5V 2.7V-5.5V
Note 1. /xxx stands for the ROM code name assigned by STMicroelectronics Note 2. Devices with E Suffix have no embedded LVD
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Customer Address
ST7265x MICROCONTROLLER OPTION LIST ................................................................. ................................................................. ................................................................. Contact ................................................................. Phone No . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference/ROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *ROM code name is assigned by STMicroelectronics. ROM code must be sent in .S19 format. .Hex extension cannot be processed. STMicroelectronics references: Device Type/Memory Size/Package (check only one option):
--------------------------------- | ---------------------------------------------------- | -----------------------------------------ROM DEVICE: 16K (without low voltage feature) 32K --------------------------------- | ---------------------------------------------------- | ------------------------------------------
TQFP64: TQFP48: SO34:
| | |
[ ] ST72652AR4T1 [ ] ST72652C4T1 [ ] ST72652L4M1
| | |
[ ] ST72651AR6T1
Conditioning (check only one option): [ ] Tray LVD option:
Marking:
[ ] Tape & Reel [ ] Yes [ ] No
[ ] Standard marking [ ] Special marking: TQFP64 (10 char. max): _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. Pull-up on PE5: Power Supply mode: [ ] Disabled [ ] Stand-alone mode [ ] Dual supply mode [ ] USB mode [ ] Software Activation [ ] Disabled [ ] Disabled [ ] STMicroelectronics [ ] Hardware Activation [ ] Enabled [ ] Enabled [ ] Customer [ ] External laboratory [ ] Enabled
Watchdog Selection: USBEN alternate function: Readout Protection: Software Development:
Comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................................................. Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notes ................................................................. ................................................................. Date ................................................................. Signature .................................................................
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15.3 DEVELOPMENT TOOLS STmicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site: http//mcu.st.com. Tools from these manufacturers include C compliers, emulators and gang programmers. Table 39. STMicroelectronics Tool Features
In-Circuit Emulation ST7 FLASH HDS2 Emulator 3) Yes, powerful emulation features including trace/ logic analyzer Programming Capability1) No Yes Sales Type ST7MDTU5-EMU2B ST7MDTU5-EPB/EU ST7MDTU5-EPB/US See 3rd Party ST7-HICROSS ST7-HIWAVE 220V 110V TQFP64 package for PC for PC Remarks
STMicroelectronics Tools Three types of development tool are offered by ST, all of them connect to a PC via a parallel (LPT) or USB port: see Table 39 for more details.
ST7 Programming No Board 3) Gang Programmer C Hiware Compiler Hiware Debugger
Note:
1. In-Application Programming (IAP) and In-Circuit programming for Flash devices. 2. These products come with a CD ROM which contains the following software: - ST7 Assembly toolchain - STVD7 and WGDB7 powerful Source Level Debugger for Win 3.1, Win 95 and NT - C compiler demo versions - ST Realizer for Win 3.1 and Win 95 - Windows Programming Tools for Win 3.1, Win 95 and NT 3. TQFP64 package only.
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15.4 ST7 APPLICATION NOTES
IDENTIFICATION DESCRIPTION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 IC COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR IC SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF IC BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS AN1130 WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264 PRODUCT OPTIMIZATION
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DESCRIPTION USING ST7 WITH CERAMIC RENATOR HOW TO MINIMIZE THE ST7 POWER CONSUMPTION SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES ST7 CHECKSUM SELF-CHECKING CAPABILITY CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS EMULATED DATA EEPROM WITH XFLASH MEMORY EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILAN1530 LATOR PROGRAMMING AND TOOLS AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PROAN1179 GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IDENTIFICATION AN 982 AN1014 AN1015 AN1040 AN1070 AN1324 AN1477 AN1502 AN1529
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16 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision Main changes Added TQFP48 and SO34 packages Changed device summary Changed section 4.4 on page 22: "and the device can be reprogrammed" added Added Section 4.7 "Related Documentation" on page 24 Changed section 7 on page 41: removed reference to EICR register (ISx bits are in the MISCR1 and MISCR3 registers and not in the EICR register). Changed section 9.1 on page 49: added an important note Changed section 9.2.4 on page 53: removed references to a second solution when using bit manipulation Changed section 9.4 on page 54: modified description of D[7:0] bits Added text specifying that the watchdog counter is a free-running downcounter: Section 11.1.2 and section 11.1.3 on page 58 Added the following tables: "FLASH Register Map and Reset Values" on page 24, "Miscellaneous Register Map and Reset Values" on page 57 and "16-Bit Timer Register Map and Reset Values" on page 91 Added Section 11.3.5 and section 11.3.6 on page 70 Removed reference to PWM mode and One Pulse mode in the description of OLVL2 and OCIE bits in section 11.4.6 on page 88 Updated section 11.6.5.4 on page 104 (removed reference to multimaster system) Removed reference to BUSY flag in section 11.7.2 on page 109 Removed reference to BUSY bit and BERR bit in Table 34, "I2C Register Map," on page 117 Added Section 11.7.5 and section 11.7.6 on page 113 Changed section 13.3.1 on page 130 and Figure 74 Changed section 13.7.1 on page 137 and added section 13.7.2 on page 138 Changed section 14 on page 156 Updated description of option byte 0 (section 15.1 on page 159) Changed section 15.2 on page 160 and section 15.3 on page 162 Please read carefully Section 9 I/O PORTS Date
2.3
June 03
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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